491 	unsigned int reg, reg_val;  in xgbe_disable_tx_flow_control()  local
503 		reg_val = XGMAC_IOREAD(pdata, reg);  in xgbe_disable_tx_flow_control()
504 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);  in xgbe_disable_tx_flow_control()
505 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_disable_tx_flow_control()
517 	unsigned int reg, reg_val;  in xgbe_enable_tx_flow_control()  local
541 		reg_val = XGMAC_IOREAD(pdata, reg);  in xgbe_enable_tx_flow_control()
544 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);  in xgbe_enable_tx_flow_control()
547 		XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);  in xgbe_enable_tx_flow_control()
549 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_enable_tx_flow_control()
1238 	unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R);  in xgbe_set_ext_mii_mode()  local
1244 		reg_val |= (1 << port);  in xgbe_set_ext_mii_mode()
1252 	XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val);  in xgbe_set_ext_mii_mode()
1956 	unsigned int i, j, reg, reg_val;  in xgbe_config_queue_mapping()  local
1986 	reg_val = 0;  in xgbe_config_queue_mapping()
2001 		reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));  in xgbe_config_queue_mapping()
2006 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_config_queue_mapping()
2008 		reg_val = 0;  in xgbe_config_queue_mapping()
2013 	reg_val = 0;  in xgbe_config_queue_mapping()
2015 		reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));  in xgbe_config_queue_mapping()
2020 		XGMAC_IOWRITE(pdata, reg, reg_val);  in xgbe_config_queue_mapping()
2023 		reg_val = 0;  in xgbe_config_queue_mapping()
2600 	unsigned int reg_val, i;  in xgbe_enable_rx()  local
2611 	reg_val = 0;  in xgbe_enable_rx()
2613 		reg_val |= (0x02 << (i << 1));  in xgbe_enable_rx()
2614 	XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);  in xgbe_enable_rx()