39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,  in rtw89_mac_mem_write()  argument
44 	rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr);  in rtw89_mac_mem_write()
45 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val);  in rtw89_mac_mem_write()
48 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,  in rtw89_mac_mem_read()  argument
53 	rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr);  in rtw89_mac_mem_read()
54 	return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY);  in rtw89_mac_mem_read()
57 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx,  in rtw89_mac_check_mac_en()  argument
63 		r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN);  in rtw89_mac_check_mac_en()
66 		r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN);  in rtw89_mac_check_mac_en()
69 		r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND);  in rtw89_mac_check_mac_en()
81 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)  in rtw89_mac_write_lte()  argument
87 				50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);  in rtw89_mac_write_lte()
89 		rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");  in rtw89_mac_write_lte()
91 	rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);  in rtw89_mac_write_lte()
92 	rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset);  in rtw89_mac_write_lte()
97 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)  in rtw89_mac_read_lte()  argument
103 				50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);  in rtw89_mac_read_lte()
105 		rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");  in rtw89_mac_read_lte()
107 	rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset);  in rtw89_mac_read_lte()
108 	*val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);  in rtw89_mac_read_lte()
114 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)  in dle_dfi_ctrl()  argument
136 		rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);  in dle_dfi_ctrl()
140 	rtw89_write32(rtwdev, ctrl_reg, ctrl_data);  in dle_dfi_ctrl()
143 				       1, 1000, false, rtwdev, ctrl_reg);  in dle_dfi_ctrl()
145 		rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",  in dle_dfi_ctrl()
150 	ctrl->out_data = rtw89_read32(rtwdev, data_reg);  in dle_dfi_ctrl()
154 static int dle_dfi_quota(struct rtw89_dev *rtwdev,  in dle_dfi_quota()  argument
163 	ret = dle_dfi_ctrl(rtwdev, &ctrl);  in dle_dfi_quota()
165 		rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);  in dle_dfi_quota()
174 static int dle_dfi_qempty(struct rtw89_dev *rtwdev,  in dle_dfi_qempty()  argument
183 	ret = dle_dfi_ctrl(rtwdev, &ctrl);  in dle_dfi_qempty()
185 		rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);  in dle_dfi_qempty()
193 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev)  in dump_err_status_dispatcher()  argument
195 	rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ",  in dump_err_status_dispatcher()
196 		   rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));  in dump_err_status_dispatcher()
197 	rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n",  in dump_err_status_dispatcher()
198 		   rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));  in dump_err_status_dispatcher()
199 	rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ",  in dump_err_status_dispatcher()
200 		   rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));  in dump_err_status_dispatcher()
201 	rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n",  in dump_err_status_dispatcher()
202 		   rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));  in dump_err_status_dispatcher()
203 	rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ",  in dump_err_status_dispatcher()
204 		   rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));  in dump_err_status_dispatcher()
205 	rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n",  in dump_err_status_dispatcher()
206 		   rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));  in dump_err_status_dispatcher()
209 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev)  in rtw89_mac_dump_qta_lost()  argument
220 	ret = dle_dfi_qempty(rtwdev, &qempty);  in rtw89_mac_dump_qta_lost()
222 		rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);  in rtw89_mac_dump_qta_lost()
224 		rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);  in rtw89_mac_dump_qta_lost()
233 		ret = dle_dfi_ctrl(rtwdev, &ctrl);  in rtw89_mac_dump_qta_lost()
235 			rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);  in rtw89_mac_dump_qta_lost()
237 			rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i,  in rtw89_mac_dump_qta_lost()
244 	ret = dle_dfi_quota(rtwdev, &quota);  in rtw89_mac_dump_qta_lost()
246 		rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);  in rtw89_mac_dump_qta_lost()
248 		rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",  in rtw89_mac_dump_qta_lost()
251 	val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);  in rtw89_mac_dump_qta_lost()
252 	rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n",  in rtw89_mac_dump_qta_lost()
254 	rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n",  in rtw89_mac_dump_qta_lost()
257 	dump_err_status_dispatcher(rtwdev);  in rtw89_mac_dump_qta_lost()
260 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,  in rtw89_mac_dump_l0_to_l1()  argument
265 	dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);  in rtw89_mac_dump_l0_to_l1()
270 		rtw89_info(rtwdev, "quota lost!\n");  in rtw89_mac_dump_l0_to_l1()
271 		rtw89_mac_dump_qta_lost(rtwdev);  in rtw89_mac_dump_l0_to_l1()
278 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev)  in rtw89_mac_dump_dmac_err_status()  argument
280 	const struct rtw89_chip_info *chip = rtwdev->chip;  in rtw89_mac_dump_dmac_err_status()
284 	ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);  in rtw89_mac_dump_dmac_err_status()
286 		rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n");  in rtw89_mac_dump_dmac_err_status()
290 	dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);  in rtw89_mac_dump_dmac_err_status()
291 	rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);  in rtw89_mac_dump_dmac_err_status()
292 	rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
293 		   rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
296 		rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
297 			   rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));  in rtw89_mac_dump_dmac_err_status()
298 		rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
299 			   rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));  in rtw89_mac_dump_dmac_err_status()
301 			rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
302 				   rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));  in rtw89_mac_dump_dmac_err_status()
303 			rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
304 				   rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));  in rtw89_mac_dump_dmac_err_status()
305 			rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
306 				   rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));  in rtw89_mac_dump_dmac_err_status()
307 			rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
308 				   rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));  in rtw89_mac_dump_dmac_err_status()
313 		rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
314 			   rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
315 		rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
316 			   rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
318 			rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
319 				   rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));  in rtw89_mac_dump_dmac_err_status()
321 			rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
322 				   rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));  in rtw89_mac_dump_dmac_err_status()
327 			rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
328 				   rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));  in rtw89_mac_dump_dmac_err_status()
329 			rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
330 				   rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));  in rtw89_mac_dump_dmac_err_status()
331 			rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
332 				   rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));  in rtw89_mac_dump_dmac_err_status()
333 			rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
334 				   rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));  in rtw89_mac_dump_dmac_err_status()
335 			rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
336 				   rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));  in rtw89_mac_dump_dmac_err_status()
337 			rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
338 				   rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));  in rtw89_mac_dump_dmac_err_status()
339 			rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
340 				   rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));  in rtw89_mac_dump_dmac_err_status()
341 			rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
342 				   rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));  in rtw89_mac_dump_dmac_err_status()
343 			rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
344 				   rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));  in rtw89_mac_dump_dmac_err_status()
346 			rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,  in rtw89_mac_dump_dmac_err_status()
348 			rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,  in rtw89_mac_dump_dmac_err_status()
350 			rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,  in rtw89_mac_dump_dmac_err_status()
353 				rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,  in rtw89_mac_dump_dmac_err_status()
355 				rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
356 					   i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));  in rtw89_mac_dump_dmac_err_status()
359 			rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
360 				   rtw89_read32(rtwdev, R_AX_SEC_DEBUG));  in rtw89_mac_dump_dmac_err_status()
361 			rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
362 				   rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));  in rtw89_mac_dump_dmac_err_status()
363 			rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
364 				   rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));  in rtw89_mac_dump_dmac_err_status()
365 			rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
366 				   rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));  in rtw89_mac_dump_dmac_err_status()
367 			rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
368 				   rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));  in rtw89_mac_dump_dmac_err_status()
369 			rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
370 				   rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));  in rtw89_mac_dump_dmac_err_status()
371 			rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
372 				   rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));  in rtw89_mac_dump_dmac_err_status()
373 			rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
374 				   rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));  in rtw89_mac_dump_dmac_err_status()
375 			rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
376 				   rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));  in rtw89_mac_dump_dmac_err_status()
377 			rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
378 				   rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));  in rtw89_mac_dump_dmac_err_status()
383 		rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
384 			   rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
385 		rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
386 			   rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
387 		rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
388 			   rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
389 		rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
390 			   rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
394 		rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
395 			   rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
396 		rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
397 			   rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
401 		rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
402 			   rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
403 		rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
404 			   rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
405 		rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
406 			   rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
407 		rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
408 			   rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));  in rtw89_mac_dump_dmac_err_status()
413 			rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
414 				   rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));  in rtw89_mac_dump_dmac_err_status()
415 			rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
416 				   rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));  in rtw89_mac_dump_dmac_err_status()
417 			rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
418 				   rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));  in rtw89_mac_dump_dmac_err_status()
419 			rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
420 				   rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));  in rtw89_mac_dump_dmac_err_status()
422 			rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
423 				   rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));  in rtw89_mac_dump_dmac_err_status()
424 			rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
425 				   rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));  in rtw89_mac_dump_dmac_err_status()
430 		rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
431 			   rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
432 		rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
433 			   rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
434 		rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
435 			   rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
436 		rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
437 			   rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));  in rtw89_mac_dump_dmac_err_status()
438 		rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
439 			   rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));  in rtw89_mac_dump_dmac_err_status()
440 		rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
441 			   rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));  in rtw89_mac_dump_dmac_err_status()
442 		rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
443 			   rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));  in rtw89_mac_dump_dmac_err_status()
444 		rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
445 			   rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));  in rtw89_mac_dump_dmac_err_status()
446 		rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
447 			   rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));  in rtw89_mac_dump_dmac_err_status()
448 		rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
449 			   rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));  in rtw89_mac_dump_dmac_err_status()
450 		rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
451 			   rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));  in rtw89_mac_dump_dmac_err_status()
452 		rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
453 			   rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));  in rtw89_mac_dump_dmac_err_status()
455 			rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
456 				   rtw89_read32(rtwdev, R_AX_RX_CTRL0));  in rtw89_mac_dump_dmac_err_status()
457 			rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
458 				   rtw89_read32(rtwdev, R_AX_RX_CTRL1));  in rtw89_mac_dump_dmac_err_status()
459 			rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
460 				   rtw89_read32(rtwdev, R_AX_RX_CTRL2));  in rtw89_mac_dump_dmac_err_status()
462 			rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
463 				   rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));  in rtw89_mac_dump_dmac_err_status()
464 			rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
465 				   rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));  in rtw89_mac_dump_dmac_err_status()
466 			rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
467 				   rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));  in rtw89_mac_dump_dmac_err_status()
472 		rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
473 			   rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
474 		rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
475 			   rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
479 		rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
480 			   rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
481 		rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
482 			   rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
483 		rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
484 			   rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
485 		rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
486 			   rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
487 		rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
488 			   rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
489 		rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
490 			   rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
495 			rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
496 				   rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
497 			rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
498 				   rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
499 			rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
500 				   rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
501 			rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
502 				   rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
503 			rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
504 				   rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
505 			rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
506 				   rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
508 			rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
509 				   rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));  in rtw89_mac_dump_dmac_err_status()
510 			rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
511 				   rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
512 			rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
513 				   rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
514 			rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
515 				   rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));  in rtw89_mac_dump_dmac_err_status()
516 			rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
517 				   rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));  in rtw89_mac_dump_dmac_err_status()
522 		rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
523 			   rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));  in rtw89_mac_dump_dmac_err_status()
524 		rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",  in rtw89_mac_dump_dmac_err_status()
525 			   rtw89_read32(rtwdev, R_AX_HAXI_IDCT));  in rtw89_mac_dump_dmac_err_status()
529 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev,  in rtw89_mac_dump_cmac_err_status()  argument
532 	const struct rtw89_chip_info *chip = rtwdev->chip;  in rtw89_mac_dump_cmac_err_status()
537 	ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);  in rtw89_mac_dump_cmac_err_status()
540 			rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n");  in rtw89_mac_dump_cmac_err_status()
542 			rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n");  in rtw89_mac_dump_cmac_err_status()
549 	cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);  in rtw89_mac_dump_cmac_err_status()
550 	rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
551 		   rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));  in rtw89_mac_dump_cmac_err_status()
552 	rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
553 		   rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));  in rtw89_mac_dump_cmac_err_status()
554 	rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
555 		   rtw89_read32(rtwdev, R_AX_CK_EN + offset));  in rtw89_mac_dump_cmac_err_status()
558 		rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
559 			   rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));  in rtw89_mac_dump_cmac_err_status()
560 		rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
561 			   rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));  in rtw89_mac_dump_cmac_err_status()
565 		rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
566 			   rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));  in rtw89_mac_dump_cmac_err_status()
567 		rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
568 			   rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));  in rtw89_mac_dump_cmac_err_status()
573 			rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
574 				   rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));  in rtw89_mac_dump_cmac_err_status()
575 			rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
576 				   rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));  in rtw89_mac_dump_cmac_err_status()
578 			rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
579 				   rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));  in rtw89_mac_dump_cmac_err_status()
585 			rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
586 				   rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));  in rtw89_mac_dump_cmac_err_status()
587 			rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
588 				   rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));  in rtw89_mac_dump_cmac_err_status()
590 			rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
591 				   rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));  in rtw89_mac_dump_cmac_err_status()
596 		rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
597 			   rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));  in rtw89_mac_dump_cmac_err_status()
598 		rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
599 			   rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));  in rtw89_mac_dump_cmac_err_status()
604 			rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
605 				   rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));  in rtw89_mac_dump_cmac_err_status()
606 			rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
607 				   rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));  in rtw89_mac_dump_cmac_err_status()
609 			rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
610 				   rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));  in rtw89_mac_dump_cmac_err_status()
612 		rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
613 			   rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));  in rtw89_mac_dump_cmac_err_status()
616 	rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,  in rtw89_mac_dump_cmac_err_status()
617 		   rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));  in rtw89_mac_dump_cmac_err_status()
620 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,  in rtw89_mac_dump_err_status()  argument
630 	rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);  in rtw89_mac_dump_err_status()
631 	rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",  in rtw89_mac_dump_err_status()
632 		   rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));  in rtw89_mac_dump_err_status()
634 	rtw89_mac_dump_dmac_err_status(rtwdev);  in rtw89_mac_dump_err_status()
635 	rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0);  in rtw89_mac_dump_err_status()
636 	if (rtwdev->dbcc_en)  in rtw89_mac_dump_err_status()
637 		rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1);  in rtw89_mac_dump_err_status()
639 	rtwdev->hci.ops->dump_err_status(rtwdev);  in rtw89_mac_dump_err_status()
642 		rtw89_mac_dump_l0_to_l1(rtwdev, err);  in rtw89_mac_dump_err_status()
644 	rtw89_info(rtwdev, "<---\n");  in rtw89_mac_dump_err_status()
647 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err)  in rtw89_mac_suppress_log()  argument
649 	struct rtw89_ser *ser = &rtwdev->ser;  in rtw89_mac_suppress_log()
653 	if (rtwdev->chip->chip_id == RTL8852C) {  in rtw89_mac_suppress_log()
654 		ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);  in rtw89_mac_suppress_log()
659 			dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);  in rtw89_mac_suppress_log()
660 			imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);  in rtw89_mac_suppress_log()
661 			isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR);  in rtw89_mac_suppress_log()
680 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)  in rtw89_mac_get_err_status()  argument
686 				false, rtwdev, R_AX_HALT_C2H_CTRL);  in rtw89_mac_get_err_status()
688 		rtw89_warn(rtwdev, "Polling FW err status fail\n");  in rtw89_mac_get_err_status()
692 	err = rtw89_read32(rtwdev, R_AX_HALT_C2H);  in rtw89_mac_get_err_status()
693 	rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);  in rtw89_mac_get_err_status()
703 	if (rtw89_mac_suppress_log(rtwdev, err))  in rtw89_mac_get_err_status()
706 	rtw89_fw_st_dbg_dump(rtwdev);  in rtw89_mac_get_err_status()
707 	rtw89_mac_dump_err_status(rtwdev, err);  in rtw89_mac_get_err_status()
713 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)  in rtw89_mac_set_err_status()  argument
715 	struct rtw89_ser *ser = &rtwdev->ser;  in rtw89_mac_set_err_status()
720 		rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);  in rtw89_mac_set_err_status()
725 				100000, false, rtwdev, R_AX_HALT_H2C_CTRL);  in rtw89_mac_set_err_status()
727 		rtw89_err(rtwdev, "FW doesn't receive previous msg\n");  in rtw89_mac_set_err_status()
731 	rtw89_write32(rtwdev, R_AX_HALT_H2C, err);  in rtw89_mac_set_err_status()
737 	rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);  in rtw89_mac_set_err_status()
743 static int hfc_reset_param(struct rtw89_dev *rtwdev)  in hfc_reset_param()  argument
745 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_reset_param()
747 	u8 qta_mode = rtwdev->mac.dle_info.qta_mode;  in hfc_reset_param()
749 	switch (rtwdev->hci.type) {  in hfc_reset_param()
751 		param_ini = rtwdev->chip->hfc_param_ini[qta_mode];  in hfc_reset_param()
774 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)  in hfc_ch_cfg_chk()  argument
776 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_ch_cfg_chk()
793 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)  in hfc_pub_info_chk()  argument
795 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_pub_info_chk()
800 		if (rtwdev->chip->chip_id == RTL8852A)  in hfc_pub_info_chk()
809 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)  in hfc_pub_cfg_chk()  argument
811 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_pub_cfg_chk()
820 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)  in hfc_ch_ctrl()  argument
822 	const struct rtw89_chip_info *chip = rtwdev->chip;  in hfc_ch_ctrl()
824 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_ch_ctrl()
829 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in hfc_ch_ctrl()
833 	ret = hfc_ch_cfg_chk(rtwdev, ch);  in hfc_ch_ctrl()
843 	rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);  in hfc_ch_ctrl()
848 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)  in hfc_upd_ch_info()  argument
850 	const struct rtw89_chip_info *chip = rtwdev->chip;  in hfc_upd_ch_info()
852 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_upd_ch_info()
858 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in hfc_upd_ch_info()
865 	val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);  in hfc_upd_ch_info()
875 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)  in hfc_pub_ctrl()  argument
877 	const struct rtw89_chip_info *chip = rtwdev->chip;  in hfc_pub_ctrl()
879 	const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;  in hfc_pub_ctrl()
883 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in hfc_pub_ctrl()
887 	ret = hfc_pub_cfg_chk(rtwdev);  in hfc_pub_ctrl()
893 	rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);  in hfc_pub_ctrl()
896 	rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);  in hfc_pub_ctrl()
901 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)  in hfc_upd_mix_info()  argument
903 	const struct rtw89_chip_info *chip = rtwdev->chip;  in hfc_upd_mix_info()
905 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_upd_mix_info()
912 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in hfc_upd_mix_info()
916 	val = rtw89_read32(rtwdev, regs->pub_page_info1);  in hfc_upd_mix_info()
919 	val = rtw89_read32(rtwdev, regs->pub_page_info3);  in hfc_upd_mix_info()
923 		u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),  in hfc_upd_mix_info()
926 		u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),  in hfc_upd_mix_info()
929 	val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);  in hfc_upd_mix_info()
942 	val = rtw89_read32(rtwdev, regs->ch_page_ctrl);  in hfc_upd_mix_info()
946 	val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);  in hfc_upd_mix_info()
949 	val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);  in hfc_upd_mix_info()
953 	val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);  in hfc_upd_mix_info()
956 	val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);  in hfc_upd_mix_info()
960 	ret = hfc_pub_info_chk(rtwdev);  in hfc_upd_mix_info()
967 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev)  in hfc_h2c_cfg()  argument
969 	const struct rtw89_chip_info *chip = rtwdev->chip;  in hfc_h2c_cfg()
971 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_h2c_cfg()
976 	rtw89_write32(rtwdev, regs->ch_page_ctrl, val);  in hfc_h2c_cfg()
978 	rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,  in hfc_h2c_cfg()
983 static void hfc_mix_cfg(struct rtw89_dev *rtwdev)  in hfc_mix_cfg()  argument
985 	const struct rtw89_chip_info *chip = rtwdev->chip;  in hfc_mix_cfg()
987 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_mix_cfg()
994 	rtw89_write32(rtwdev, regs->ch_page_ctrl, val);  in hfc_mix_cfg()
997 	rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);  in hfc_mix_cfg()
1003 	rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);  in hfc_mix_cfg()
1005 	val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),  in hfc_mix_cfg()
1015 	rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);  in hfc_mix_cfg()
1018 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en)  in hfc_func_en()  argument
1020 	const struct rtw89_chip_info *chip = rtwdev->chip;  in hfc_func_en()
1022 	struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;  in hfc_func_en()
1025 	val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);  in hfc_func_en()
1031 	rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);  in hfc_func_en()
1034 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)  in hfc_init()  argument
1036 	const struct rtw89_chip_info *chip = rtwdev->chip;  in hfc_init()
1042 		ret = hfc_reset_param(rtwdev);  in hfc_init()
1046 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in hfc_init()
1050 	hfc_func_en(rtwdev, false, false);  in hfc_init()
1053 		hfc_h2c_cfg(rtwdev);  in hfc_init()
1054 		hfc_func_en(rtwdev, en, h2c_en);  in hfc_init()
1061 		ret = hfc_ch_ctrl(rtwdev, ch);  in hfc_init()
1066 	ret = hfc_pub_ctrl(rtwdev);  in hfc_init()
1070 	hfc_mix_cfg(rtwdev);  in hfc_init()
1072 		hfc_func_en(rtwdev, en, h2c_en);  in hfc_init()
1078 		ret = hfc_upd_ch_info(rtwdev, ch);  in hfc_init()
1082 	ret = hfc_upd_mix_info(rtwdev);  in hfc_init()
1088 static int pwr_cmd_poll(struct rtw89_dev *rtwdev,  in pwr_cmd_poll()  argument
1097 				1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);  in pwr_cmd_poll()
1102 	rtw89_warn(rtwdev, "[ERR] Polling timeout\n");  in pwr_cmd_poll()
1103 	rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);  in pwr_cmd_poll()
1104 	rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);  in pwr_cmd_poll()
1109 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,  in rtw89_mac_sub_pwr_seq()  argument
1128 			val = rtw89_read8(rtwdev, addr);  in rtw89_mac_sub_pwr_seq()
1132 			rtw89_write8(rtwdev, addr, val);  in rtw89_mac_sub_pwr_seq()
1135 			if (pwr_cmd_poll(rtwdev, cur_cfg))  in rtw89_mac_sub_pwr_seq()
1152 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,  in rtw89_mac_pwr_seq()  argument
1158 		ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),  in rtw89_mac_pwr_seq()
1168 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)  in rtw89_mac_get_req_pwr_state()  argument
1172 	switch (rtwdev->ps_mode) {  in rtw89_mac_get_req_pwr_state()
1189 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,  in rtw89_mac_send_rpwm()  argument
1195 	spin_lock_bh(&rtwdev->rpwm_lock);  in rtw89_mac_send_rpwm()
1197 	request = rtw89_read16(rtwdev, R_AX_RPWM);  in rtw89_mac_send_rpwm()
1204 		rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &  in rtw89_mac_send_rpwm()
1207 				      rtwdev->mac.rpwm_seq_num);  in rtw89_mac_send_rpwm()
1212 	rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);  in rtw89_mac_send_rpwm()
1214 	spin_unlock_bh(&rtwdev->rpwm_lock);  in rtw89_mac_send_rpwm()
1217 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,  in rtw89_mac_check_cpwm_state()  argument
1232 	if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))  in rtw89_mac_check_cpwm_state()
1243 	rpwm_req_num = rtwdev->mac.rpwm_seq_num;  in rtw89_mac_check_cpwm_state()
1244 	cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,  in rtw89_mac_check_cpwm_state()
1250 	rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &  in rtw89_mac_check_cpwm_state()
1253 	cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);  in rtw89_mac_check_cpwm_state()
1254 	if (cpwm_seq != rtwdev->mac.cpwm_seq_num)  in rtw89_mac_check_cpwm_state()
1257 	cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);  in rtw89_mac_check_cpwm_state()
1264 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter)  in rtw89_mac_power_mode_change()  argument
1272 		state = rtw89_mac_get_req_pwr_state(rtwdev);  in rtw89_mac_power_mode_change()
1277 		rtw89_mac_send_rpwm(rtwdev, state, false);  in rtw89_mac_power_mode_change()
1280 					       rtwdev, state);  in rtw89_mac_power_mode_change()
1285 			rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n",  in rtw89_mac_power_mode_change()
1288 			rtw89_debug(rtwdev, RTW89_DBG_UNEXP,  in rtw89_mac_power_mode_change()
1294 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev)  in rtw89_mac_notify_wake()  argument
1298 	state = rtw89_mac_get_req_pwr_state(rtwdev);  in rtw89_mac_notify_wake()
1299 	rtw89_mac_send_rpwm(rtwdev, state, true);  in rtw89_mac_notify_wake()
1302 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)  in rtw89_mac_power_switch()  argument
1305 	const struct rtw89_chip_info *chip = rtwdev->chip;  in rtw89_mac_power_switch()
1307 	int (*cfg_func)(struct rtw89_dev *rtwdev);  in rtw89_mac_power_switch()
1319 	if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))  in rtw89_mac_power_switch()
1320 		__rtw89_leave_ps_mode(rtwdev);  in rtw89_mac_power_switch()
1322 	val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);  in rtw89_mac_power_switch()
1324 		rtw89_err(rtwdev, "MAC has already powered on\n");  in rtw89_mac_power_switch()
1328 	ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq);  in rtw89_mac_power_switch()
1333 		set_bit(RTW89_FLAG_POWERON, rtwdev->flags);  in rtw89_mac_power_switch()
1334 		rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);  in rtw89_mac_power_switch()
1336 		clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);  in rtw89_mac_power_switch()
1337 		clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);  in rtw89_mac_power_switch()
1338 		rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);  in rtw89_mac_power_switch()
1339 		rtw89_set_entity_state(rtwdev, false);  in rtw89_mac_power_switch()
1346 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev)  in rtw89_mac_pwr_off()  argument
1348 	rtw89_mac_power_switch(rtwdev, false);  in rtw89_mac_pwr_off()
1351 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)  in cmac_func_en()  argument
1374 			rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en);  in cmac_func_en()
1375 			rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,  in cmac_func_en()
1377 			rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,  in cmac_func_en()
1380 		rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en);  in cmac_func_en()
1381 		rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en);  in cmac_func_en()
1383 		rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en);  in cmac_func_en()
1384 		rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en);  in cmac_func_en()
1386 			rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,  in cmac_func_en()
1388 			rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,  in cmac_func_en()
1390 			rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en);  in cmac_func_en()
1397 static int dmac_func_en(struct rtw89_dev *rtwdev)  in dmac_func_en()  argument
1399 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in dmac_func_en()
1418 	rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32);  in dmac_func_en()
1424 	rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32);  in dmac_func_en()
1429 static int chip_func_en(struct rtw89_dev *rtwdev)  in chip_func_en()  argument
1431 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in chip_func_en()
1434 		rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,  in chip_func_en()
1440 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev)  in rtw89_mac_sys_init()  argument
1444 	ret = dmac_func_en(rtwdev);  in rtw89_mac_sys_init()
1448 	ret = cmac_func_en(rtwdev, 0, true);  in rtw89_mac_sys_init()
1452 	ret = chip_func_en(rtwdev);  in rtw89_mac_sys_init()
1526 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,  in get_dle_mem_cfg()  argument
1529 	struct rtw89_mac_info *mac = &rtwdev->mac;  in get_dle_mem_cfg()
1532 	cfg = &rtwdev->chip->dle_mem[mode];  in get_dle_mem_cfg()
1537 		rtw89_warn(rtwdev, "qta mode unmatch!\n");  in get_dle_mem_cfg()
1549 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev)  in mac_is_txq_empty()  argument
1555 	qnum = rtwdev->chip->wde_qempty_acq_num;  in mac_is_txq_empty()
1560 		ret = dle_dfi_qempty(rtwdev, &qempty);  in mac_is_txq_empty()
1562 			rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret);  in mac_is_txq_empty()
1574 	qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel;  in mac_is_txq_empty()
1575 	ret = dle_dfi_qempty(rtwdev, &qempty);  in mac_is_txq_empty()
1577 		rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret);  in mac_is_txq_empty()
1584 	if (rtwdev->dbcc_en) {  in mac_is_txq_empty()
1598 	val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);  in mac_is_txq_empty()
1610 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,  in dle_expected_used_size()  argument
1613 	u32 size = rtwdev->chip->fifo_size;  in dle_expected_used_size()
1616 		size -= rtwdev->chip->dle_scc_rsvd_size;  in dle_expected_used_size()
1621 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable)  in dle_func_en()  argument
1624 		rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,  in dle_func_en()
1627 		rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN,  in dle_func_en()
1631 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable)  in dle_clk_en()  argument
1636 		if (rtwdev->chip->chip_id == RTL8851B)  in dle_clk_en()
1638 		rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val);  in dle_clk_en()
1640 		rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val);  in dle_clk_en()
1644 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)  in dle_mix_cfg()  argument
1650 	val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);  in dle_mix_cfg()
1664 		rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");  in dle_mix_cfg()
1671 	rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);  in dle_mix_cfg()
1673 	val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);  in dle_mix_cfg()
1681 		rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");  in dle_mix_cfg()
1696 	rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);  in dle_mix_cfg()
1706 		rtw89_write32(rtwdev,					\
1713 static void wde_quota_cfg(struct rtw89_dev *rtwdev,  in wde_quota_cfg()  argument
1728 static void ple_quota_cfg(struct rtw89_dev *rtwdev,  in ple_quota_cfg()  argument
1745 	if (rtwdev->chip->chip_id == RTL8852C)  in ple_quota_cfg()
1749 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)  in rtw89_mac_resize_ple_rx_quota()  argument
1755 	if (rtwdev->chip->chip_id == RTL8852C)  in rtw89_mac_resize_ple_rx_quota()
1758 	if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {  in rtw89_mac_resize_ple_rx_quota()
1759 		rtw89_err(rtwdev, "[ERR]support SCC mode only\n");  in rtw89_mac_resize_ple_rx_quota()
1764 		cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW);  in rtw89_mac_resize_ple_rx_quota()
1766 		cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC);  in rtw89_mac_resize_ple_rx_quota()
1768 		rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");  in rtw89_mac_resize_ple_rx_quota()
1781 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable)  in rtw89_mac_hw_mgnt_sec()  argument
1786 		rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32);  in rtw89_mac_hw_mgnt_sec()
1788 		rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32);  in rtw89_mac_hw_mgnt_sec()
1791 static void dle_quota_cfg(struct rtw89_dev *rtwdev,  in dle_quota_cfg()  argument
1795 	wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);  in dle_quota_cfg()
1796 	ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);  in dle_quota_cfg()
1799 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,  in dle_init()  argument
1807 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in dle_init()
1811 	cfg = get_dle_mem_cfg(rtwdev, mode);  in dle_init()
1813 		rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");  in dle_init()
1819 		ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode);  in dle_init()
1821 			rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n",  in dle_init()
1830 	    dle_expected_used_size(rtwdev, mode)) {  in dle_init()
1831 		rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");  in dle_init()
1836 	dle_func_en(rtwdev, false);  in dle_init()
1837 	dle_clk_en(rtwdev, true);  in dle_init()
1839 	ret = dle_mix_cfg(rtwdev, cfg);  in dle_init()
1841 		rtw89_err(rtwdev, "[ERR] dle mix cfg\n");  in dle_init()
1844 	dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu);  in dle_init()
1846 	dle_func_en(rtwdev, true);  in dle_init()
1850 				2000, false, rtwdev, R_AX_WDE_INI_STATUS);  in dle_init()
1852 		rtw89_err(rtwdev, "[ERR]WDE cfg ready\n");  in dle_init()
1858 				2000, false, rtwdev, R_AX_PLE_INI_STATUS);  in dle_init()
1860 		rtw89_err(rtwdev, "[ERR]PLE cfg ready\n");  in dle_init()
1866 	dle_func_en(rtwdev, false);  in dle_init()
1867 	rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n",  in dle_init()
1868 		  rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS));  in dle_init()
1869 	rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n",  in dle_init()
1870 		  rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS));  in dle_init()
1875 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,  in preload_init_set()  argument
1884 	rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size);  in preload_init_set()
1885 	rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN);  in preload_init_set()
1890 	rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND);  in preload_init_set()
1891 	rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size);  in preload_init_set()
1896 static bool is_qta_poh(struct rtw89_dev *rtwdev)  in is_qta_poh()  argument
1898 	return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;  in is_qta_poh()
1901 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,  in preload_init()  argument
1904 	const struct rtw89_chip_info *chip = rtwdev->chip;  in preload_init()
1907 	    chip->chip_id == RTL8851B || !is_qta_poh(rtwdev))  in preload_init()
1910 	return preload_init_set(rtwdev, mac_idx, mode);  in preload_init()
1913 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)  in dle_is_txq_empty()  argument
1931 	val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);  in dle_is_txq_empty()
1939 static void _patch_ss2f_path(struct rtw89_dev *rtwdev)  in _patch_ss2f_path()  argument
1941 	const struct rtw89_chip_info *chip = rtwdev->chip;  in _patch_ss2f_path()
1947 	rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,  in _patch_ss2f_path()
1951 static int sta_sch_init(struct rtw89_dev *rtwdev)  in sta_sch_init()  argument
1957 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in sta_sch_init()
1961 	val = rtw89_read8(rtwdev, R_AX_SS_CTRL);  in sta_sch_init()
1963 	rtw89_write8(rtwdev, R_AX_SS_CTRL, val);  in sta_sch_init()
1966 				1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL);  in sta_sch_init()
1968 		rtw89_err(rtwdev, "[ERR]STA scheduler init\n");  in sta_sch_init()
1972 	rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);  in sta_sch_init()
1973 	rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN);  in sta_sch_init()
1975 	_patch_ss2f_path(rtwdev);  in sta_sch_init()
1980 static int mpdu_proc_init(struct rtw89_dev *rtwdev)  in mpdu_proc_init()  argument
1984 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in mpdu_proc_init()
1988 	rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);  in mpdu_proc_init()
1989 	rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);  in mpdu_proc_init()
1990 	rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,  in mpdu_proc_init()
1992 	rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);  in mpdu_proc_init()
1997 static int sec_eng_init(struct rtw89_dev *rtwdev)  in sec_eng_init()  argument
1999 	const struct rtw89_chip_info *chip = rtwdev->chip;  in sec_eng_init()
2003 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in sec_eng_init()
2007 	val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);  in sec_eng_init()
2016 	rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);  in sec_eng_init()
2019 	val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);  in sec_eng_init()
2023 	rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);  in sec_eng_init()
2026 		rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,  in sec_eng_init()
2032 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in dmac_init()  argument
2036 	ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);  in dmac_init()
2038 		rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);  in dmac_init()
2042 	ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);  in dmac_init()
2044 		rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);  in dmac_init()
2048 	ret = hfc_init(rtwdev, true, true, true);  in dmac_init()
2050 		rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);  in dmac_init()
2054 	ret = sta_sch_init(rtwdev);  in dmac_init()
2056 		rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);  in dmac_init()
2060 	ret = mpdu_proc_init(rtwdev);  in dmac_init()
2062 		rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);  in dmac_init()
2066 	ret = sec_eng_init(rtwdev);  in dmac_init()
2068 		rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);  in dmac_init()
2075 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in addr_cam_init()  argument
2081 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in addr_cam_init()
2087 	val = rtw89_read32(rtwdev, reg);  in addr_cam_init()
2090 	rtw89_write32(rtwdev, reg, val);  in addr_cam_init()
2093 				1, TRXCFG_WAIT_CNT, false, rtwdev, reg);  in addr_cam_init()
2095 		rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");  in addr_cam_init()
2102 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in scheduler_init()  argument
2108 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in scheduler_init()
2113 	if (rtwdev->chip->chip_id == RTL8852C)  in scheduler_init()
2114 		rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,  in scheduler_init()
2117 		rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,  in scheduler_init()
2120 	if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) {  in scheduler_init()
2122 		rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);  in scheduler_init()
2126 	rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);  in scheduler_init()
2129 	if (rtwdev->chip->chip_id == RTL8852C) {  in scheduler_init()
2130 		val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,  in scheduler_init()
2133 			rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,  in scheduler_init()
2136 		rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,  in scheduler_init()
2143 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,  in rtw89_mac_typ_fltr_opt()  argument
2162 		rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");  in rtw89_mac_typ_fltr_opt()
2177 		rtw89_err(rtwdev, "[ERR]set rx filter type err\n");  in rtw89_mac_typ_fltr_opt()
2180 	rtw89_write32(rtwdev, reg, val);  in rtw89_mac_typ_fltr_opt()
2185 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in rx_fltr_init()  argument
2190 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rx_fltr_init()
2195 		ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST,  in rx_fltr_init()
2200 	mac_ftlr = rtwdev->hal.rx_fltr;  in rx_fltr_init()
2205 	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx),  in rx_fltr_init()
2207 	rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx),  in rx_fltr_init()
2213 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx)  in _patch_dis_resp_chk()  argument
2224 	switch (rtwdev->chip->chip_id) {  in _patch_dis_resp_chk()
2228 		val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav;  in _patch_dis_resp_chk()
2229 		rtw89_write32(rtwdev, reg, val32);  in _patch_dis_resp_chk()
2232 		val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca;  in _patch_dis_resp_chk()
2233 		rtw89_write32(rtwdev, reg, val32);  in _patch_dis_resp_chk()
2237 		val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav;  in _patch_dis_resp_chk()
2238 		rtw89_write32(rtwdev, reg, val32);  in _patch_dis_resp_chk()
2241 		val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca;  in _patch_dis_resp_chk()
2242 		rtw89_write32(rtwdev, reg, val32);  in _patch_dis_resp_chk()
2247 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in cca_ctrl_init()  argument
2252 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in cca_ctrl_init()
2257 	val = rtw89_read32(rtwdev, reg);  in cca_ctrl_init()
2272 	rtw89_write32(rtwdev, reg, val);  in cca_ctrl_init()
2274 	_patch_dis_resp_chk(rtwdev, mac_idx);  in cca_ctrl_init()
2279 static int nav_ctrl_init(struct rtw89_dev *rtwdev)  in nav_ctrl_init()  argument
2281 	rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |  in nav_ctrl_init()
2284 	rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS);  in nav_ctrl_init()
2289 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in spatial_reuse_init()  argument
2294 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in spatial_reuse_init()
2298 	rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);  in spatial_reuse_init()
2303 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in tmac_init()  argument
2308 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in tmac_init()
2313 	rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);  in tmac_init()
2316 	rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD);  in tmac_init()
2319 	rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);  in tmac_init()
2320 	rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);  in tmac_init()
2325 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in trxptcl_init()  argument
2327 	const struct rtw89_chip_info *chip = rtwdev->chip;  in trxptcl_init()
2332 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in trxptcl_init()
2337 	val = rtw89_read32(rtwdev, reg);  in trxptcl_init()
2341 	switch (rtwdev->chip->chip_id) {  in trxptcl_init()
2354 	rtw89_write32(rtwdev, reg, val);  in trxptcl_init()
2357 	rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);  in trxptcl_init()
2360 	rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);  in trxptcl_init()
2362 	rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);  in trxptcl_init()
2367 static void rst_bacam(struct rtw89_dev *rtwdev)  in rst_bacam()  argument
2372 	rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK,  in rst_bacam()
2377 				       rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK);  in rst_bacam()
2379 		rtw89_warn(rtwdev, "failed to reset BA CAM\n");  in rst_bacam()
2382 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in rmac_init()  argument
2393 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rmac_init()
2398 		rst_bacam(rtwdev);  in rmac_init()
2401 	rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);  in rmac_init()
2404 	val = rtw89_read16(rtwdev, reg);  in rmac_init()
2409 	rtw89_write16(rtwdev, reg, val);  in rmac_init()
2412 	rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1);  in rmac_init()
2416 		rx_qta = rtwdev->mac.dle_info.c0_rx_qta;  in rmac_init()
2418 		rx_qta = rtwdev->mac.dle_info.c1_rx_qta;  in rmac_init()
2420 	rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;  in rmac_init()
2423 	rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len);  in rmac_init()
2425 	if (rtwdev->chip->chip_id == RTL8852A &&  in rmac_init()
2426 	    rtwdev->hal.cv == CHIP_CBV) {  in rmac_init()
2427 		rtw89_write16_mask(rtwdev,  in rmac_init()
2430 		rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx),  in rmac_init()
2435 	rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);  in rmac_init()
2440 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in cmac_com_init()  argument
2442 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in cmac_com_init()
2446 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in cmac_com_init()
2451 	val = rtw89_read32(rtwdev, reg);  in cmac_com_init()
2455 	rtw89_write32(rtwdev, reg, val);  in cmac_com_init()
2459 		rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);  in cmac_com_init()
2465 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)  in is_qta_dbcc()  argument
2469 	cfg = get_dle_mem_cfg(rtwdev, mode);  in is_qta_dbcc()
2471 		rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");  in is_qta_dbcc()
2478 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in ptcl_init()  argument
2483 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in ptcl_init()
2487 	if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {  in ptcl_init()
2489 		val = rtw89_read32(rtwdev, reg);  in ptcl_init()
2495 		rtw89_write32(rtwdev, reg, val);  in ptcl_init()
2498 		val = rtw89_read32(rtwdev, reg);  in ptcl_init()
2501 		rtw89_write32(rtwdev, reg, val);  in ptcl_init()
2505 		rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0,  in ptcl_init()
2507 		rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0,  in ptcl_init()
2511 		rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL,  in ptcl_init()
2514 		rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1,  in ptcl_init()
2521 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in cmac_dma_init()  argument
2523 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in cmac_dma_init()
2530 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in cmac_dma_init()
2535 	rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE);  in cmac_dma_init()
2540 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)  in cmac_init()  argument
2544 	ret = scheduler_init(rtwdev, mac_idx);  in cmac_init()
2546 		rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);  in cmac_init()
2550 	ret = addr_cam_init(rtwdev, mac_idx);  in cmac_init()
2552 		rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,  in cmac_init()
2557 	ret = rx_fltr_init(rtwdev, mac_idx);  in cmac_init()
2559 		rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,  in cmac_init()
2564 	ret = cca_ctrl_init(rtwdev, mac_idx);  in cmac_init()
2566 		rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,  in cmac_init()
2571 	ret = nav_ctrl_init(rtwdev);  in cmac_init()
2573 		rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,  in cmac_init()
2578 	ret = spatial_reuse_init(rtwdev, mac_idx);  in cmac_init()
2580 		rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",  in cmac_init()
2585 	ret = tmac_init(rtwdev, mac_idx);  in cmac_init()
2587 		rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);  in cmac_init()
2591 	ret = trxptcl_init(rtwdev, mac_idx);  in cmac_init()
2593 		rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);  in cmac_init()
2597 	ret = rmac_init(rtwdev, mac_idx);  in cmac_init()
2599 		rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);  in cmac_init()
2603 	ret = cmac_com_init(rtwdev, mac_idx);  in cmac_init()
2605 		rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);  in cmac_init()
2609 	ret = ptcl_init(rtwdev, mac_idx);  in cmac_init()
2611 		rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);  in cmac_init()
2615 	ret = cmac_dma_init(rtwdev, mac_idx);  in cmac_init()
2617 		rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);  in cmac_init()
2624 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,  in rtw89_mac_read_phycap()  argument
2633 	ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info);  in rtw89_mac_read_phycap()
2643 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)  in rtw89_mac_setup_phycap()  argument
2645 	struct rtw89_efuse *efuse = &rtwdev->efuse;  in rtw89_mac_setup_phycap()
2646 	struct rtw89_hal *hal = &rtwdev->hal;  in rtw89_mac_setup_phycap()
2647 	const struct rtw89_chip_info *chip = rtwdev->chip;  in rtw89_mac_setup_phycap()
2656 	ret = rtw89_mac_read_phycap(rtwdev, &c2h_info);  in rtw89_mac_setup_phycap()
2687 	rtw89_debug(rtwdev, RTW89_DBG_FW,  in rtw89_mac_setup_phycap()
2691 	rtw89_debug(rtwdev, RTW89_DBG_FW,  in rtw89_mac_setup_phycap()
2694 	rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);  in rtw89_mac_setup_phycap()
2695 	rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);  in rtw89_mac_setup_phycap()
2700 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,  in rtw89_hw_sch_tx_en_h2c()  argument
2715 	ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);  in rtw89_hw_sch_tx_en_h2c()
2725 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,  in rtw89_set_hw_sch_tx_en()  argument
2732 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_set_hw_sch_tx_en()
2736 	if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))  in rtw89_set_hw_sch_tx_en()
2737 		return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx,  in rtw89_set_hw_sch_tx_en()
2740 	val = rtw89_read16(rtwdev, reg);  in rtw89_set_hw_sch_tx_en()
2742 	rtw89_write16(rtwdev, reg, val);  in rtw89_set_hw_sch_tx_en()
2747 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx,  in rtw89_set_hw_sch_tx_en_v1()  argument
2754 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_set_hw_sch_tx_en_v1()
2758 	val = rtw89_read32(rtwdev, reg);  in rtw89_set_hw_sch_tx_en_v1()
2760 	rtw89_write32(rtwdev, reg, val);  in rtw89_set_hw_sch_tx_en_v1()
2765 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,  in rtw89_mac_stop_sch_tx()  argument
2770 	*tx_en = rtw89_read16(rtwdev,  in rtw89_mac_stop_sch_tx()
2775 		ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,  in rtw89_mac_stop_sch_tx()
2781 		ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,  in rtw89_mac_stop_sch_tx()
2787 		ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,  in rtw89_mac_stop_sch_tx()
2793 		ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,  in rtw89_mac_stop_sch_tx()
2806 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,  in rtw89_mac_stop_sch_tx_v1()  argument
2811 	*tx_en = rtw89_read32(rtwdev,  in rtw89_mac_stop_sch_tx_v1()
2816 		ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,  in rtw89_mac_stop_sch_tx_v1()
2822 		ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,  in rtw89_mac_stop_sch_tx_v1()
2828 		ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,  in rtw89_mac_stop_sch_tx_v1()
2834 		ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,  in rtw89_mac_stop_sch_tx_v1()
2847 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)  in rtw89_mac_resume_sch_tx()  argument
2851 	ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK);  in rtw89_mac_resume_sch_tx()
2859 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)  in rtw89_mac_resume_sch_tx_v1()  argument
2863 	ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en,  in rtw89_mac_resume_sch_tx_v1()
2872 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id)  in rtw89_mac_dle_buf_req()  argument
2880 	rtw89_write32(rtwdev, reg, val);  in rtw89_mac_dle_buf_req()
2885 				1, 2000, false, rtwdev, reg);  in rtw89_mac_dle_buf_req()
2896 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,  in rtw89_mac_set_cpuio()  argument
2910 	rtw89_write32(rtwdev, reg, val);  in rtw89_mac_set_cpuio()
2922 	rtw89_write32(rtwdev, reg, val);  in rtw89_mac_set_cpuio()
2933 	rtw89_write32(rtwdev, reg, val);  in rtw89_mac_set_cpuio()
2938 				1, 2000, false, rtwdev, reg);  in rtw89_mac_set_cpuio()
2949 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)  in dle_quota_change()  argument
2956 	cfg = get_dle_mem_cfg(rtwdev, mode);  in dle_quota_change()
2958 		rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");  in dle_quota_change()
2963 	    dle_expected_used_size(rtwdev, mode)) {  in dle_quota_change()
2964 		rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");  in dle_quota_change()
2968 	dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU);  in dle_quota_change()
2970 	ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id);  in dle_quota_change()
2972 		rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n");  in dle_quota_change()
2982 	ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true);  in dle_quota_change()
2984 		rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n");  in dle_quota_change()
2988 	ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id);  in dle_quota_change()
2990 		rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n");  in dle_quota_change()
3000 	ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false);  in dle_quota_change()
3002 		rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n");  in dle_quota_change()
3009 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx)  in band_idle_ck_b()  argument
3015 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in band_idle_ck_b()
3025 				false, rtwdev, reg);  in band_idle_ck_b()
3032 static int band1_enable(struct rtw89_dev *rtwdev)  in band1_enable()  argument
3039 	ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL);  in band1_enable()
3041 		rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret);  in band1_enable()
3046 		sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4);  in band1_enable()
3047 		pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4);  in band1_enable()
3048 		rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX);  in band1_enable()
3049 		rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX);  in band1_enable()
3052 	ret = band_idle_ck_b(rtwdev, 0);  in band1_enable()
3054 		rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);  in band1_enable()
3058 	ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode);  in band1_enable()
3060 		rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);  in band1_enable()
3065 		rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]);  in band1_enable()
3066 		rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]);  in band1_enable()
3069 	ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en);  in band1_enable()
3071 		rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret);  in band1_enable()
3075 	ret = cmac_func_en(rtwdev, 1, true);  in band1_enable()
3077 		rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret);  in band1_enable()
3081 	ret = cmac_init(rtwdev, 1);  in band1_enable()
3083 		rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret);  in band1_enable()
3087 	rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,  in band1_enable()
3093 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_wdrls_imr_enable()  argument
3095 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_wdrls_imr_enable()
3097 	rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR);  in rtw89_wdrls_imr_enable()
3098 	rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);  in rtw89_wdrls_imr_enable()
3101 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_wsec_imr_enable()  argument
3103 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_wsec_imr_enable()
3105 	rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);  in rtw89_wsec_imr_enable()
3108 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_mpdu_trx_imr_enable()  argument
3110 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in rtw89_mpdu_trx_imr_enable()
3111 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_mpdu_trx_imr_enable()
3113 	rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,  in rtw89_mpdu_trx_imr_enable()
3120 		rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,  in rtw89_mpdu_trx_imr_enable()
3125 	rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,  in rtw89_mpdu_trx_imr_enable()
3128 	rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR,  in rtw89_mpdu_trx_imr_enable()
3132 	rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,  in rtw89_mpdu_trx_imr_enable()
3136 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_sta_sch_imr_enable()  argument
3138 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_sta_sch_imr_enable()
3140 	rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,  in rtw89_sta_sch_imr_enable()
3144 	rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,  in rtw89_sta_sch_imr_enable()
3148 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_txpktctl_imr_enable()  argument
3150 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_txpktctl_imr_enable()
3152 	rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,  in rtw89_txpktctl_imr_enable()
3154 	rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,  in rtw89_txpktctl_imr_enable()
3156 	rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,  in rtw89_txpktctl_imr_enable()
3158 	rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,  in rtw89_txpktctl_imr_enable()
3162 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_wde_imr_enable()  argument
3164 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_wde_imr_enable()
3166 	rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);  in rtw89_wde_imr_enable()
3167 	rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);  in rtw89_wde_imr_enable()
3170 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_ple_imr_enable()  argument
3172 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_ple_imr_enable()
3174 	rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);  in rtw89_ple_imr_enable()
3175 	rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);  in rtw89_ple_imr_enable()
3178 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_pktin_imr_enable()  argument
3180 	rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,  in rtw89_pktin_imr_enable()
3184 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_dispatcher_imr_enable()  argument
3186 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_dispatcher_imr_enable()
3188 	rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
3190 	rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
3192 	rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
3194 	rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
3196 	rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
3198 	rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,  in rtw89_dispatcher_imr_enable()
3202 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_cpuio_imr_enable()  argument
3204 	rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR);  in rtw89_cpuio_imr_enable()
3205 	rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);  in rtw89_cpuio_imr_enable()
3208 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)  in rtw89_bbrpt_imr_enable()  argument
3210 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_bbrpt_imr_enable()
3212 	rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,  in rtw89_bbrpt_imr_enable()
3214 	rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,  in rtw89_bbrpt_imr_enable()
3216 	rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,  in rtw89_bbrpt_imr_enable()
3218 	rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,  in rtw89_bbrpt_imr_enable()
3220 	rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);  in rtw89_bbrpt_imr_enable()
3223 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)  in rtw89_scheduler_imr_enable()  argument
3228 	rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |  in rtw89_scheduler_imr_enable()
3230 	rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);  in rtw89_scheduler_imr_enable()
3233 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)  in rtw89_ptcl_imr_enable()  argument
3235 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_ptcl_imr_enable()
3239 	rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);  in rtw89_ptcl_imr_enable()
3240 	rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);  in rtw89_ptcl_imr_enable()
3243 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)  in rtw89_cdma_imr_enable()  argument
3245 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_cdma_imr_enable()
3246 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in rtw89_cdma_imr_enable()
3250 	rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);  in rtw89_cdma_imr_enable()
3251 	rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);  in rtw89_cdma_imr_enable()
3255 		rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);  in rtw89_cdma_imr_enable()
3256 		rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);  in rtw89_cdma_imr_enable()
3260 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)  in rtw89_phy_intf_imr_enable()  argument
3262 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_phy_intf_imr_enable()
3266 	rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);  in rtw89_phy_intf_imr_enable()
3267 	rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);  in rtw89_phy_intf_imr_enable()
3270 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)  in rtw89_rmac_imr_enable()  argument
3272 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_rmac_imr_enable()
3276 	rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);  in rtw89_rmac_imr_enable()
3277 	rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);  in rtw89_rmac_imr_enable()
3280 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)  in rtw89_tmac_imr_enable()  argument
3282 	const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;  in rtw89_tmac_imr_enable()
3286 	rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);  in rtw89_tmac_imr_enable()
3287 	rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);  in rtw89_tmac_imr_enable()
3290 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,  in rtw89_mac_enable_imr()  argument
3295 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);  in rtw89_mac_enable_imr()
3297 		rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n",  in rtw89_mac_enable_imr()
3303 		rtw89_wdrls_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3304 		rtw89_wsec_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3305 		rtw89_mpdu_trx_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3306 		rtw89_sta_sch_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3307 		rtw89_txpktctl_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3308 		rtw89_wde_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3309 		rtw89_ple_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3310 		rtw89_pktin_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3311 		rtw89_dispatcher_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3312 		rtw89_cpuio_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3313 		rtw89_bbrpt_imr_enable(rtwdev);  in rtw89_mac_enable_imr()
3315 		rtw89_scheduler_imr_enable(rtwdev, mac_idx);  in rtw89_mac_enable_imr()
3316 		rtw89_ptcl_imr_enable(rtwdev, mac_idx);  in rtw89_mac_enable_imr()
3317 		rtw89_cdma_imr_enable(rtwdev, mac_idx);  in rtw89_mac_enable_imr()
3318 		rtw89_phy_intf_imr_enable(rtwdev, mac_idx);  in rtw89_mac_enable_imr()
3319 		rtw89_rmac_imr_enable(rtwdev, mac_idx);  in rtw89_mac_enable_imr()
3320 		rtw89_tmac_imr_enable(rtwdev, mac_idx);  in rtw89_mac_enable_imr()
3328 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en)  in rtw89_mac_err_imr_ctrl()  argument
3330 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in rtw89_mac_err_imr_ctrl()
3332 	rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR,  in rtw89_mac_err_imr_ctrl()
3334 	rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR,  in rtw89_mac_err_imr_ctrl()
3336 	if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta)  in rtw89_mac_err_imr_ctrl()
3337 		rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1,  in rtw89_mac_err_imr_ctrl()
3341 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable)  in rtw89_mac_dbcc_enable()  argument
3346 		ret = band1_enable(rtwdev);  in rtw89_mac_dbcc_enable()
3348 			rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);  in rtw89_mac_dbcc_enable()
3352 		ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);  in rtw89_mac_dbcc_enable()
3354 			rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);  in rtw89_mac_dbcc_enable()
3358 		rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n");  in rtw89_mac_dbcc_enable()
3365 static int set_host_rpr(struct rtw89_dev *rtwdev)  in set_host_rpr()  argument
3367 	if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {  in set_host_rpr()
3368 		rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,  in set_host_rpr()
3370 		rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0,  in set_host_rpr()
3373 		rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,  in set_host_rpr()
3375 		rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0,  in set_host_rpr()
3379 	rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30);  in set_host_rpr()
3380 	rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255);  in set_host_rpr()
3385 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev)  in rtw89_mac_trx_init()  argument
3387 	enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;  in rtw89_mac_trx_init()
3390 	ret = dmac_init(rtwdev, 0);  in rtw89_mac_trx_init()
3392 		rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);  in rtw89_mac_trx_init()
3396 	ret = cmac_init(rtwdev, 0);  in rtw89_mac_trx_init()
3398 		rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);  in rtw89_mac_trx_init()
3402 	if (is_qta_dbcc(rtwdev, qta_mode)) {  in rtw89_mac_trx_init()
3403 		ret = rtw89_mac_dbcc_enable(rtwdev, true);  in rtw89_mac_trx_init()
3405 			rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);  in rtw89_mac_trx_init()
3410 	ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);  in rtw89_mac_trx_init()
3412 		rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);  in rtw89_mac_trx_init()
3416 	ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);  in rtw89_mac_trx_init()
3418 		rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);  in rtw89_mac_trx_init()
3422 	rtw89_mac_err_imr_ctrl(rtwdev, true);  in rtw89_mac_trx_init()
3424 	ret = set_host_rpr(rtwdev);  in rtw89_mac_trx_init()
3426 		rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);  in rtw89_mac_trx_init()
3433 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)  in rtw89_disable_fw_watchdog()  argument
3435 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in rtw89_disable_fw_watchdog()
3439 		rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);  in rtw89_disable_fw_watchdog()
3440 		rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);  in rtw89_disable_fw_watchdog()
3444 	rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL,  in rtw89_disable_fw_watchdog()
3447 	val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL);  in rtw89_disable_fw_watchdog()
3450 	rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);  in rtw89_disable_fw_watchdog()
3453 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)  in rtw89_mac_disable_cpu()  argument
3455 	clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);  in rtw89_mac_disable_cpu()
3457 	rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);  in rtw89_mac_disable_cpu()
3458 	rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN |  in rtw89_mac_disable_cpu()
3460 	rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);  in rtw89_mac_disable_cpu()
3462 	rtw89_disable_fw_watchdog(rtwdev);  in rtw89_mac_disable_cpu()
3464 	rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);  in rtw89_mac_disable_cpu()
3465 	rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);  in rtw89_mac_disable_cpu()
3468 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)  in rtw89_mac_enable_cpu()  argument
3473 	if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)  in rtw89_mac_enable_cpu()
3476 	rtw89_write32(rtwdev, R_AX_UDM1, 0);  in rtw89_mac_enable_cpu()
3477 	rtw89_write32(rtwdev, R_AX_UDM2, 0);  in rtw89_mac_enable_cpu()
3478 	rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);  in rtw89_mac_enable_cpu()
3479 	rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);  in rtw89_mac_enable_cpu()
3480 	rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);  in rtw89_mac_enable_cpu()
3481 	rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);  in rtw89_mac_enable_cpu()
3483 	rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);  in rtw89_mac_enable_cpu()
3485 	val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);  in rtw89_mac_enable_cpu()
3493 	rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);  in rtw89_mac_enable_cpu()
3495 	if (rtwdev->chip->chip_id == RTL8852B)  in rtw89_mac_enable_cpu()
3496 		rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL,  in rtw89_mac_enable_cpu()
3499 	rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK,  in rtw89_mac_enable_cpu()
3501 	rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);  in rtw89_mac_enable_cpu()
3506 		ret = rtw89_fw_check_rdy(rtwdev);  in rtw89_mac_enable_cpu()
3514 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev)  in rtw89_mac_dmac_pre_init()  argument
3516 	enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;  in rtw89_mac_dmac_pre_init()
3526 	rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);  in rtw89_mac_dmac_pre_init()
3532 	rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);  in rtw89_mac_dmac_pre_init()
3537 	val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);  in rtw89_mac_dmac_pre_init()
3541 	rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);  in rtw89_mac_dmac_pre_init()
3543 	rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1,  in rtw89_mac_dmac_pre_init()
3548 	rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11);  in rtw89_mac_dmac_pre_init()
3549 	rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN);  in rtw89_mac_dmac_pre_init()
3552 	ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);  in rtw89_mac_dmac_pre_init()
3554 		rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret);  in rtw89_mac_dmac_pre_init()
3558 	ret = hfc_init(rtwdev, true, false, true);  in rtw89_mac_dmac_pre_init()
3560 		rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret);  in rtw89_mac_dmac_pre_init()
3567 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)  in rtw89_mac_enable_bb_rf()  argument
3569 	rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,  in rtw89_mac_enable_bb_rf()
3571 	rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL,  in rtw89_mac_enable_bb_rf()
3574 	rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);  in rtw89_mac_enable_bb_rf()
3580 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)  in rtw89_mac_disable_bb_rf()  argument
3582 	rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,  in rtw89_mac_disable_bb_rf()
3584 	rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL,  in rtw89_mac_disable_bb_rf()
3587 	rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);  in rtw89_mac_disable_bb_rf()
3593 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev)  in rtw89_mac_partial_init()  argument
3597 	ret = rtw89_mac_power_switch(rtwdev, true);  in rtw89_mac_partial_init()
3599 		rtw89_mac_power_switch(rtwdev, false);  in rtw89_mac_partial_init()
3600 		ret = rtw89_mac_power_switch(rtwdev, true);  in rtw89_mac_partial_init()
3605 	rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);  in rtw89_mac_partial_init()
3607 	ret = rtw89_mac_dmac_pre_init(rtwdev);  in rtw89_mac_partial_init()
3611 	if (rtwdev->hci.ops->mac_pre_init) {  in rtw89_mac_partial_init()
3612 		ret = rtwdev->hci.ops->mac_pre_init(rtwdev);  in rtw89_mac_partial_init()
3617 	ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL);  in rtw89_mac_partial_init()
3624 int rtw89_mac_init(struct rtw89_dev *rtwdev)  in rtw89_mac_init()  argument
3628 	ret = rtw89_mac_partial_init(rtwdev);  in rtw89_mac_init()
3632 	ret = rtw89_chip_enable_bb_rf(rtwdev);  in rtw89_mac_init()
3636 	ret = rtw89_mac_sys_init(rtwdev);  in rtw89_mac_init()
3640 	ret = rtw89_mac_trx_init(rtwdev);  in rtw89_mac_init()
3644 	if (rtwdev->hci.ops->mac_post_init) {  in rtw89_mac_init()
3645 		ret = rtwdev->hci.ops->mac_post_init(rtwdev);  in rtw89_mac_init()
3650 	rtw89_fw_send_all_early_h2c(rtwdev);  in rtw89_mac_init()
3651 	rtw89_fw_h2c_set_ofld_cfg(rtwdev);  in rtw89_mac_init()
3655 	rtw89_mac_power_switch(rtwdev, false);  in rtw89_mac_init()
3660 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)  in rtw89_mac_dmac_tbl_init()  argument
3665 		rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,  in rtw89_mac_dmac_tbl_init()
3667 		rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0);  in rtw89_mac_dmac_tbl_init()
3671 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)  in rtw89_mac_cmac_tbl_init()  argument
3673 	rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,  in rtw89_mac_cmac_tbl_init()
3675 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4);  in rtw89_mac_cmac_tbl_init()
3676 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004);  in rtw89_mac_cmac_tbl_init()
3677 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0);  in rtw89_mac_cmac_tbl_init()
3678 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0);  in rtw89_mac_cmac_tbl_init()
3679 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0);  in rtw89_mac_cmac_tbl_init()
3680 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B);  in rtw89_mac_cmac_tbl_init()
3681 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0);  in rtw89_mac_cmac_tbl_init()
3682 	rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109);  in rtw89_mac_cmac_tbl_init()
3685 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause)  in rtw89_mac_set_macid_pause()  argument
3694 	if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&  in rtw89_mac_set_macid_pause()
3695 	    !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))  in rtw89_mac_set_macid_pause()
3698 	ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);  in rtw89_mac_set_macid_pause()
3702 	rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause);  in rtw89_mac_set_macid_pause()
3734 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_func_sw()  argument
3740 	if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN))  in rtw89_mac_port_cfg_func_sw()
3743 	rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK);  in rtw89_mac_port_cfg_func_sw()
3744 	rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1);  in rtw89_mac_port_cfg_func_sw()
3745 	rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK);  in rtw89_mac_port_cfg_func_sw()
3746 	rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK);  in rtw89_mac_port_cfg_func_sw()
3750 	rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN |  in rtw89_mac_port_cfg_func_sw()
3752 	rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST);  in rtw89_mac_port_cfg_func_sw()
3753 	rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0);  in rtw89_mac_port_cfg_func_sw()
3756 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_tx_rpt()  argument
3762 		rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);  in rtw89_mac_port_cfg_tx_rpt()
3764 		rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);  in rtw89_mac_port_cfg_tx_rpt()
3767 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_rx_rpt()  argument
3773 		rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);  in rtw89_mac_port_cfg_rx_rpt()
3775 		rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);  in rtw89_mac_port_cfg_rx_rpt()
3778 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_net_type()  argument
3783 	rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK,  in rtw89_mac_port_cfg_net_type()
3787 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_bcn_prct()  argument
3795 		rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits);  in rtw89_mac_port_cfg_bcn_prct()
3797 		rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits);  in rtw89_mac_port_cfg_bcn_prct()
3800 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_rx_sw()  argument
3809 		rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit);  in rtw89_mac_port_cfg_rx_sw()
3811 		rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit);  in rtw89_mac_port_cfg_rx_sw()
3814 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_rx_sync()  argument
3822 		rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);  in rtw89_mac_port_cfg_rx_sync()
3824 		rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);  in rtw89_mac_port_cfg_rx_sync()
3827 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_tx_sw()  argument
3835 		rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);  in rtw89_mac_port_cfg_tx_sw()
3837 		rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);  in rtw89_mac_port_cfg_tx_sw()
3840 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_bcn_intv()  argument
3847 	rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK,  in rtw89_mac_port_cfg_bcn_intv()
3851 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_hiq_win()  argument
3864 	rtw89_write8(rtwdev, reg, win);  in rtw89_mac_port_cfg_hiq_win()
3867 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_hiq_dtim()  argument
3875 	rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);  in rtw89_mac_port_cfg_hiq_dtim()
3877 	rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,  in rtw89_mac_port_cfg_hiq_dtim()
3881 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_bcn_setup_time()  argument
3886 	rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,  in rtw89_mac_port_cfg_bcn_setup_time()
3890 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_bcn_hold_time()  argument
3895 	rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,  in rtw89_mac_port_cfg_bcn_hold_time()
3899 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_bcn_mask_area()  argument
3904 	rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area,  in rtw89_mac_port_cfg_bcn_mask_area()
3908 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_tbtt_early()  argument
3913 	rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early,  in rtw89_mac_port_cfg_tbtt_early()
3917 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_bss_color()  argument
3934 	rtw89_write32_mask(rtwdev, reg, masks[port], bss_color);  in rtw89_mac_port_cfg_bss_color()
3937 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_mbssid()  argument
3948 		rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK);  in rtw89_mac_port_cfg_mbssid()
3952 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_hiq_drop()  argument
3960 	val = rtw89_read32(rtwdev, reg);  in rtw89_mac_port_cfg_hiq_drop()
3964 	rtw89_write32(rtwdev, reg, val);  in rtw89_mac_port_cfg_hiq_drop()
3967 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_func_en()  argument
3973 		rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg,  in rtw89_mac_port_cfg_func_en()
3976 		rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg,  in rtw89_mac_port_cfg_func_en()
3980 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_bcn_early()  argument
3985 	rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK,  in rtw89_mac_port_cfg_bcn_early()
3989 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev,  in rtw89_mac_port_cfg_tbtt_shift()  argument
3995 	if (rtwdev->chip->chip_id != RTL8852C)  in rtw89_mac_port_cfg_tbtt_shift()
4005 	rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift,  in rtw89_mac_port_cfg_tbtt_shift()
4009 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,  in rtw89_mac_port_tsf_sync()  argument
4020 	rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);  in rtw89_mac_port_tsf_sync()
4021 	rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);  in rtw89_mac_port_tsf_sync()
4022 	rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW);  in rtw89_mac_port_tsf_sync()
4025 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev,  in rtw89_mac_port_tsf_sync_rand()  argument
4035 	rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src,  in rtw89_mac_port_tsf_sync_rand()
4041 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev)  in rtw89_mac_port_tsf_resync_all()  argument
4047 	rtw89_for_each_rtwvif(rtwdev, tmp) {  in rtw89_mac_port_tsf_resync_all()
4059 	rtw89_for_each_rtwvif(rtwdev, tmp)  in rtw89_mac_port_tsf_resync_all()
4060 		rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset);  in rtw89_mac_port_tsf_resync_all()
4063 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)  in rtw89_mac_vif_init()  argument
4067 	ret = rtw89_mac_port_update(rtwdev, rtwvif);  in rtw89_mac_vif_init()
4071 	rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id);  in rtw89_mac_vif_init()
4072 	rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id);  in rtw89_mac_vif_init()
4074 	ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false);  in rtw89_mac_vif_init()
4078 	ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE);  in rtw89_mac_vif_init()
4082 	ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true);  in rtw89_mac_vif_init()
4086 	ret = rtw89_cam_init(rtwdev, rtwvif);  in rtw89_mac_vif_init()
4090 	ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);  in rtw89_mac_vif_init()
4094 	ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif);  in rtw89_mac_vif_init()
4101 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)  in rtw89_mac_vif_deinit()  argument
4105 	ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE);  in rtw89_mac_vif_deinit()
4109 	rtw89_cam_deinit(rtwdev, rtwvif);  in rtw89_mac_vif_deinit()
4111 	ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);  in rtw89_mac_vif_deinit()
4118 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)  in rtw89_mac_port_update()  argument
4125 	rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif);  in rtw89_mac_port_update()
4126 	rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false);  in rtw89_mac_port_update()
4127 	rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false);  in rtw89_mac_port_update()
4128 	rtw89_mac_port_cfg_net_type(rtwdev, rtwvif);  in rtw89_mac_port_update()
4129 	rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif);  in rtw89_mac_port_update()
4130 	rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif);  in rtw89_mac_port_update()
4131 	rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif);  in rtw89_mac_port_update()
4132 	rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif);  in rtw89_mac_port_update()
4133 	rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif);  in rtw89_mac_port_update()
4134 	rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif);  in rtw89_mac_port_update()
4135 	rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif);  in rtw89_mac_port_update()
4136 	rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif);  in rtw89_mac_port_update()
4137 	rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif);  in rtw89_mac_port_update()
4138 	rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif);  in rtw89_mac_port_update()
4139 	rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif);  in rtw89_mac_port_update()
4140 	rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif);  in rtw89_mac_port_update()
4141 	rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif);  in rtw89_mac_port_update()
4142 	rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);  in rtw89_mac_port_update()
4143 	rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);  in rtw89_mac_port_update()
4144 	rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true);  in rtw89_mac_port_update()
4145 	rtw89_mac_port_tsf_resync_all(rtwdev);  in rtw89_mac_port_update()
4147 	rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);  in rtw89_mac_port_update()
4152 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,  in rtw89_mac_port_get_tsf()  argument
4159 	ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL);  in rtw89_mac_port_get_tsf()
4163 	tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l);  in rtw89_mac_port_get_tsf()
4164 	tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h);  in rtw89_mac_port_get_tsf()
4189 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,  in rtw89_mac_set_he_obss_narrow_bw_ru()  argument
4193 	struct ieee80211_hw *hw = rtwdev->hw;  in rtw89_mac_set_he_obss_narrow_bw_ru()
4209 		rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);  in rtw89_mac_set_he_obss_narrow_bw_ru()
4211 		rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);  in rtw89_mac_set_he_obss_narrow_bw_ru()
4214 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)  in rtw89_mac_stop_ap()  argument
4216 	rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false);  in rtw89_mac_stop_ap()
4219 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)  in rtw89_mac_add_vif()  argument
4223 	rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,  in rtw89_mac_add_vif()
4228 	ret = rtw89_mac_vif_init(rtwdev, rtwvif);  in rtw89_mac_add_vif()
4235 	rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);  in rtw89_mac_add_vif()
4240 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)  in rtw89_mac_remove_vif()  argument
4244 	ret = rtw89_mac_vif_deinit(rtwdev, rtwvif);  in rtw89_mac_remove_vif()
4245 	rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);  in rtw89_mac_remove_vif()
4251 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)  in rtw89_mac_c2h_macid_pause()  argument
4255 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel)  in rtw89_is_op_chan()  argument
4257 	const struct rtw89_chan *op = &rtwdev->scan_info.op_chan;  in rtw89_is_op_chan()
4263 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h,  in rtw89_mac_c2h_scanofld_rsp()  argument
4266 	struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;  in rtw89_mac_c2h_scanofld_rsp()
4270 	u32 last_chan = rtwdev->scan_info.last_chan_idx;  in rtw89_mac_c2h_scanofld_rsp()
4284 	if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))  in rtw89_mac_c2h_scanofld_rsp()
4287 	rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,  in rtw89_mac_c2h_scanofld_rsp()
4293 		if (rtw89_is_op_chan(rtwdev, band, chan))  in rtw89_mac_c2h_scanofld_rsp()
4294 			ieee80211_stop_queues(rtwdev->hw);  in rtw89_mac_c2h_scanofld_rsp()
4299 			ret = rtw89_hw_scan_offload(rtwdev, vif, true);  in rtw89_mac_c2h_scanofld_rsp()
4301 				rtw89_hw_scan_abort(rtwdev, vif);  in rtw89_mac_c2h_scanofld_rsp()
4302 				rtw89_warn(rtwdev, "HW scan failed: %d\n", ret);  in rtw89_mac_c2h_scanofld_rsp()
4305 			rtw89_hw_scan_complete(rtwdev, vif, false);  in rtw89_mac_c2h_scanofld_rsp()
4309 		if (rtw89_is_op_chan(rtwdev, band, chan)) {  in rtw89_mac_c2h_scanofld_rsp()
4310 			rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,  in rtw89_mac_c2h_scanofld_rsp()
4311 						 &rtwdev->scan_info.op_chan);  in rtw89_mac_c2h_scanofld_rsp()
4312 			ieee80211_wake_queues(rtwdev->hw);  in rtw89_mac_c2h_scanofld_rsp()
4316 			rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,  in rtw89_mac_c2h_scanofld_rsp()
4326 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,  in rtw89_mac_bcn_fltr_rpt()  argument
4344 	rtw89_debug(rtwdev, RTW89_DBG_FW,  in rtw89_mac_bcn_fltr_rpt()
4350 		if (!rtwdev->scanning && !rtwvif->offchan)  in rtw89_mac_bcn_fltr_rpt()
4353 			rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true);  in rtw89_mac_bcn_fltr_rpt()
4374 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,  in rtw89_mac_c2h_bcn_fltr_rpt()  argument
4379 	rtw89_for_each_rtwvif(rtwdev, rtwvif)  in rtw89_mac_c2h_bcn_fltr_rpt()
4380 		rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h);  in rtw89_mac_c2h_bcn_fltr_rpt()
4384 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)  in rtw89_mac_c2h_rec_ack()  argument
4388 	rtw89_debug(rtwdev, RTW89_DBG_FW,  in rtw89_mac_c2h_rec_ack()
4397 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)  in rtw89_mac_c2h_done_ack()  argument
4400 	struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;  in rtw89_mac_c2h_done_ack()
4411 	rtw89_debug(rtwdev, RTW89_DBG_FW,  in rtw89_mac_c2h_done_ack()
4438 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)  in rtw89_mac_c2h_log()  argument
4440 	rtw89_fw_log_dump(rtwdev, c2h->data, len);  in rtw89_mac_c2h_log()
4444 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)  in rtw89_mac_c2h_bcn_cnt()  argument
4449 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h,  in rtw89_mac_c2h_pkt_ofld_rsp()  argument
4452 	struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;  in rtw89_mac_c2h_pkt_ofld_rsp()
4461 	rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n",  in rtw89_mac_c2h_pkt_ofld_rsp()
4471 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,  in rtw89_mac_c2h_tsf32_toggle_rpt()  argument
4477 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)  in rtw89_mac_c2h_mcc_rcv_ack()  argument
4494 		rtw89_debug(rtwdev, RTW89_DBG_CHAN,  in rtw89_mac_c2h_mcc_rcv_ack()
4499 	rtw89_debug(rtwdev, RTW89_DBG_CHAN,  in rtw89_mac_c2h_mcc_rcv_ack()
4504 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)  in rtw89_mac_c2h_mcc_req_ack()  argument
4527 		rtw89_debug(rtwdev, RTW89_DBG_CHAN,  in rtw89_mac_c2h_mcc_req_ack()
4532 	rtw89_debug(rtwdev, RTW89_DBG_CHAN,  in rtw89_mac_c2h_mcc_req_ack()
4541 	rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);  in rtw89_mac_c2h_mcc_req_ack()
4545 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)  in rtw89_mac_c2h_mcc_tsf_rpt()  argument
4560 	rtw89_debug(rtwdev, RTW89_DBG_CHAN,  in rtw89_mac_c2h_mcc_tsf_rpt()
4572 	rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);  in rtw89_mac_c2h_mcc_tsf_rpt()
4576 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)  in rtw89_mac_c2h_mcc_status_rpt()  argument
4628 		rtw89_debug(rtwdev, RTW89_DBG_CHAN,  in rtw89_mac_c2h_mcc_status_rpt()
4633 	rtw89_debug(rtwdev, RTW89_DBG_CHAN,  in rtw89_mac_c2h_mcc_status_rpt()
4647 	rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);  in rtw89_mac_c2h_mcc_status_rpt()
4651 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
4664 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
4673 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev,
4681 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)  in rtw89_mac_c2h_chk_atomic()  argument
4706 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,  in rtw89_mac_c2h_handle()  argument
4709 	void (*handler)(struct rtw89_dev *rtwdev,  in rtw89_mac_c2h_handle()
4728 		rtw89_info(rtwdev, "c2h class %d not support\n", class);  in rtw89_mac_c2h_handle()
4732 		rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,  in rtw89_mac_c2h_handle()
4736 	handler(rtwdev, skb, len);  in rtw89_mac_c2h_handle()
4739 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,  in rtw89_mac_get_txpwr_cr()  argument
4743 	const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem;  in rtw89_mac_get_txpwr_cr()
4748 		rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",  in rtw89_mac_get_txpwr_cr()
4755 			rtw89_err(rtwdev,  in rtw89_mac_get_txpwr_cr()
4765 	rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",  in rtw89_mac_get_txpwr_cr()
4772 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)  in rtw89_mac_cfg_ppdu_status()  argument
4777 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_mac_cfg_ppdu_status()
4782 		rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN);  in rtw89_mac_cfg_ppdu_status()
4786 	rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN |  in rtw89_mac_cfg_ppdu_status()
4790 	rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,  in rtw89_mac_cfg_ppdu_status()
4797 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)  in rtw89_mac_update_rts_threshold()  argument
4805 	struct ieee80211_hw *hw = rtwdev->hw;  in rtw89_mac_update_rts_threshold()
4822 	rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th);  in rtw89_mac_update_rts_threshold()
4823 	rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th);  in rtw89_mac_update_rts_threshold()
4826 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)  in rtw89_mac_flush_txq()  argument
4831 	if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))  in rtw89_mac_flush_txq()
4835 				10000, 200000, false, rtwdev);  in rtw89_mac_flush_txq()
4836 	if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))  in rtw89_mac_flush_txq()
4837 		rtw89_info(rtwdev, "timed out to flush queues\n");  in rtw89_mac_flush_txq()
4840 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)  in rtw89_mac_coex_init()  argument
4847 	rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT);  in rtw89_mac_coex_init()
4848 	if (rtwdev->chip->chip_id != RTL8851B)  in rtw89_mac_coex_init()
4849 		rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN);  in rtw89_mac_coex_init()
4850 	rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8);  in rtw89_mac_coex_init()
4851 	rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);  in rtw89_mac_coex_init()
4852 	rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16);  in rtw89_mac_coex_init()
4853 	if (rtwdev->chip->chip_id != RTL8851B)  in rtw89_mac_coex_init()
4854 		rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24);  in rtw89_mac_coex_init()
4856 	val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0);  in rtw89_mac_coex_init()
4858 	rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16);  in rtw89_mac_coex_init()
4860 	ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32);  in rtw89_mac_coex_init()
4862 		rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n");  in rtw89_mac_coex_init()
4866 	ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32);  in rtw89_mac_coex_init()
4868 		rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n");  in rtw89_mac_coex_init()
4874 		val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);  in rtw89_mac_coex_init()
4877 		rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);  in rtw89_mac_coex_init()
4879 		val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);  in rtw89_mac_coex_init()
4880 		rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);  in rtw89_mac_coex_init()
4882 		val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);  in rtw89_mac_coex_init()
4885 		rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);  in rtw89_mac_coex_init()
4888 		val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);  in rtw89_mac_coex_init()
4891 		rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);  in rtw89_mac_coex_init()
4893 		val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE);  in rtw89_mac_coex_init()
4901 		rtw89_write16(rtwdev, R_AX_CSR_MODE, val16);  in rtw89_mac_coex_init()
4903 		rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);  in rtw89_mac_coex_init()
4911 		val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);  in rtw89_mac_coex_init()
4913 		rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);  in rtw89_mac_coex_init()
4916 		val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);  in rtw89_mac_coex_init()
4918 		rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);  in rtw89_mac_coex_init()
4921 		val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);  in rtw89_mac_coex_init()
4923 		rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);  in rtw89_mac_coex_init()
4933 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,  in rtw89_mac_coex_init_v1()  argument
4936 	rtw89_write32_set(rtwdev, R_AX_BTC_CFG,  in rtw89_mac_coex_init_v1()
4938 	rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);  in rtw89_mac_coex_init_v1()
4939 	rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);  in rtw89_mac_coex_init_v1()
4940 	rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN);  in rtw89_mac_coex_init_v1()
4944 		rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,  in rtw89_mac_coex_init_v1()
4946 		rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1,  in rtw89_mac_coex_init_v1()
4950 		rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,  in rtw89_mac_coex_init_v1()
4961 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,  in rtw89_mac_cfg_gnt()  argument
4990 	ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);  in rtw89_mac_cfg_gnt()
4992 		rtw89_err(rtwdev, "Write LTE fail!\n");  in rtw89_mac_cfg_gnt()
5000 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,  in rtw89_mac_cfg_gnt_v1()  argument
5041 	rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);  in rtw89_mac_cfg_gnt_v1()
5047 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)  in rtw89_mac_cfg_plt()  argument
5053 	ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);  in rtw89_mac_cfg_plt()
5067 	rtw89_write16(rtwdev, reg, val);  in rtw89_mac_cfg_plt()
5072 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)  in rtw89_mac_cfg_sb()  argument
5076 	fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);  in rtw89_mac_cfg_sb()
5079 	if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))  in rtw89_mac_cfg_sb()
5087 	rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);  in rtw89_mac_cfg_sb()
5091 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)  in rtw89_mac_get_sb()  argument
5093 	return rtw89_read32(rtwdev, R_AX_SCOREBOARD);  in rtw89_mac_get_sb()
5096 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)  in rtw89_mac_cfg_ctrl_path()  argument
5098 	u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);  in rtw89_mac_cfg_ctrl_path()
5101 	rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);  in rtw89_mac_cfg_ctrl_path()
5107 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl)  in rtw89_mac_cfg_ctrl_path_v1()  argument
5109 	struct rtw89_btc *btc = &rtwdev->btc;  in rtw89_mac_cfg_ctrl_path_v1()
5124 	return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);  in rtw89_mac_cfg_ctrl_path_v1()
5128 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)  in rtw89_mac_get_ctrl_path()  argument
5130 	const struct rtw89_chip_info *chip = rtwdev->chip;  in rtw89_mac_get_ctrl_path()
5136 		val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3,  in rtw89_mac_get_ctrl_path()
5142 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)  in rtw89_mac_get_plt_cnt()  argument
5148 	cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);  in rtw89_mac_get_plt_cnt()
5149 	rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);  in rtw89_mac_get_plt_cnt()
5154 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx,  in rtw89_mac_bfee_standby_timer()  argument
5159 	rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep);  in rtw89_mac_bfee_standby_timer()
5162 		set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);  in rtw89_mac_bfee_standby_timer()
5163 		rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,  in rtw89_mac_bfee_standby_timer()
5166 		clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);  in rtw89_mac_bfee_standby_timer()
5167 		rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,  in rtw89_mac_bfee_standby_timer()
5172 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)  in rtw89_mac_bfee_ctrl()  argument
5178 	rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);  in rtw89_mac_bfee_ctrl()
5181 		set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);  in rtw89_mac_bfee_ctrl()
5182 		rtw89_write32_set(rtwdev, reg, mask);  in rtw89_mac_bfee_ctrl()
5184 		clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);  in rtw89_mac_bfee_ctrl()
5185 		rtw89_write32_clr(rtwdev, reg, mask);  in rtw89_mac_bfee_ctrl()
5189 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx)  in rtw89_mac_init_bfee()  argument
5195 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_mac_init_bfee()
5202 	rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);  in rtw89_mac_init_bfee()
5205 	rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);  in rtw89_mac_init_bfee()
5209 	rtw89_write32(rtwdev, reg, val32);  in rtw89_mac_init_bfee()
5210 	rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true);  in rtw89_mac_init_bfee()
5211 	rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);  in rtw89_mac_init_bfee()
5214 	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |  in rtw89_mac_init_bfee()
5219 	rtw89_write32(rtwdev, reg,  in rtw89_mac_init_bfee()
5225 	rtw89_write32_set(rtwdev, reg,  in rtw89_mac_init_bfee()
5231 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev,  in rtw89_mac_set_csi_para_reg()  argument
5245 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_mac_set_csi_para_reg()
5269 	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);  in rtw89_mac_set_csi_para_reg()
5284 	rtw89_write16(rtwdev, reg, val);  in rtw89_mac_set_csi_para_reg()
5289 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev,  in rtw89_mac_csi_rrsc()  argument
5299 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_mac_csi_rrsc()
5319 	rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);  in rtw89_mac_csi_rrsc()
5320 	rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN);  in rtw89_mac_csi_rrsc()
5321 	rtw89_write32(rtwdev,  in rtw89_mac_csi_rrsc()
5328 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,  in rtw89_mac_bf_assoc()  argument
5334 		rtw89_debug(rtwdev, RTW89_DBG_BF,  in rtw89_mac_bf_assoc()
5336 		rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx);  in rtw89_mac_bf_assoc()
5337 		rtw89_mac_set_csi_para_reg(rtwdev, vif, sta);  in rtw89_mac_bf_assoc()
5338 		rtw89_mac_csi_rrsc(rtwdev, vif, sta);  in rtw89_mac_bf_assoc()
5342 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,  in rtw89_mac_bf_disassoc()  argument
5347 	rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false);  in rtw89_mac_bf_disassoc()
5350 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,  in rtw89_mac_bf_set_gid_table()  argument
5357 	rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n");  in rtw89_mac_bf_set_gid_table()
5360 	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx),  in rtw89_mac_bf_set_gid_table()
5362 	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx),  in rtw89_mac_bf_set_gid_table()
5366 	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx),  in rtw89_mac_bf_set_gid_table()
5368 	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx),  in rtw89_mac_bf_set_gid_table()
5370 	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx),  in rtw89_mac_bf_set_gid_table()
5372 	rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx),  in rtw89_mac_bf_set_gid_table()
5377 	struct rtw89_dev *rtwdev;  member
5397 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,  in rtw89_mac_bf_monitor_calc()  argument
5402 	data.rtwdev = rtwdev;  in rtw89_mac_bf_monitor_calc()
5405 	ieee80211_iterate_stations_atomic(rtwdev->hw,  in rtw89_mac_bf_monitor_calc()
5409 	rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count);  in rtw89_mac_bf_monitor_calc()
5411 		set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);  in rtw89_mac_bf_monitor_calc()
5413 		clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);  in rtw89_mac_bf_monitor_calc()
5416 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)  in _rtw89_mac_bf_monitor_track()  argument
5418 	struct rtw89_traffic_stats *stats = &rtwdev->stats;  in _rtw89_mac_bf_monitor_track()
5421 	bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);  in _rtw89_mac_bf_monitor_track()
5425 	old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);  in _rtw89_mac_bf_monitor_track()
5431 		rtw89_for_each_rtwvif(rtwdev, rtwvif)  in _rtw89_mac_bf_monitor_track()
5432 			rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx,  in _rtw89_mac_bf_monitor_track()
5439 	rtw89_for_each_rtwvif(rtwdev, rtwvif)  in _rtw89_mac_bf_monitor_track()
5440 		rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en);  in _rtw89_mac_bf_monitor_track()
5444 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,  in __rtw89_mac_set_tx_time()  argument
5455 		ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);  in __rtw89_mac_set_tx_time()
5457 		ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in __rtw89_mac_set_tx_time()
5459 			rtw89_warn(rtwdev, "failed to check cmac in set txtime\n");  in __rtw89_mac_set_tx_time()
5464 		rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK,  in __rtw89_mac_set_tx_time()
5471 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,  in rtw89_mac_set_tx_time()  argument
5478 		ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);  in rtw89_mac_set_tx_time()
5480 		ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);  in rtw89_mac_set_tx_time()
5487 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,  in rtw89_mac_get_tx_time()  argument
5497 		ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_mac_get_tx_time()
5499 			rtw89_warn(rtwdev, "failed to check cmac in tx_time\n");  in rtw89_mac_get_tx_time()
5504 		*tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5;  in rtw89_mac_get_tx_time()
5510 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,  in rtw89_mac_set_tx_retry_limit()  argument
5520 		ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);  in rtw89_mac_set_tx_retry_limit()
5522 		ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);  in rtw89_mac_set_tx_retry_limit()
5529 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,  in rtw89_mac_get_tx_retry_limit()  argument
5539 		ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_mac_get_tx_retry_limit()
5541 			rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n");  in rtw89_mac_get_tx_retry_limit()
5546 		*tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK);  in rtw89_mac_get_tx_retry_limit()
5552 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,  in rtw89_mac_set_hw_muedca_ctrl()  argument
5560 	ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);  in rtw89_mac_set_hw_muedca_ctrl()
5566 		rtw89_write16_set(rtwdev, reg, set);  in rtw89_mac_set_hw_muedca_ctrl()
5568 		rtw89_write16_clr(rtwdev, reg, set);  in rtw89_mac_set_hw_muedca_ctrl()
5573 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)  in rtw89_mac_write_xtal_si()  argument
5583 	rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);  in rtw89_mac_write_xtal_si()
5586 				50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);  in rtw89_mac_write_xtal_si()
5588 		rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",  in rtw89_mac_write_xtal_si()
5597 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)  in rtw89_mac_read_xtal_si()  argument
5607 	rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);  in rtw89_mac_read_xtal_si()
5610 				50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);  in rtw89_mac_read_xtal_si()
5612 		rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);  in rtw89_mac_read_xtal_si()
5616 	*val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);  in rtw89_mac_read_xtal_si()
5623 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)  in rtw89_mac_pkt_drop_sta()  argument
5643 		rtw89_fw_h2c_pkt_drop(rtwdev, &params);  in rtw89_mac_pkt_drop_sta()
5651 	struct rtw89_dev *rtwdev = rtwvif->rtwdev;  in rtw89_mac_pkt_drop_vif_iter()  local
5657 	rtw89_mac_pkt_drop_sta(rtwdev, rtwsta);  in rtw89_mac_pkt_drop_vif_iter()
5660 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)  in rtw89_mac_pkt_drop_vif()  argument
5662 	ieee80211_iterate_stations_atomic(rtwdev->hw,  in rtw89_mac_pkt_drop_vif()
5667 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,  in rtw89_mac_ptk_drop_by_band_and_wait()  argument
5679 					50000, false, rtwdev);  in rtw89_mac_ptk_drop_by_band_and_wait()
5680 		if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw))  in rtw89_mac_ptk_drop_by_band_and_wait()
5681 			rtw89_fw_h2c_pkt_drop(rtwdev, &params);  in rtw89_mac_ptk_drop_by_band_and_wait()