Lines Matching refs:WriteLatencies
60 std::vector<MCWriteLatencyEntry> WriteLatencies; member
68 WriteLatencies.resize(1); in SchedClassTables()
1112 std::vector<MCWriteLatencyEntry> WriteLatencies; in GenSchedClassTables() local
1244 WriteLatencies.push_back(WLEntry); in GenSchedClassTables()
1280 WriteLatencies.clear(); in GenSchedClassTables()
1302 SCDesc.NumWriteLatencyEntries = WriteLatencies.size(); in GenSchedClassTables()
1304 std::search(SchedTables.WriteLatencies.begin(), in GenSchedClassTables()
1305 SchedTables.WriteLatencies.end(), in GenSchedClassTables()
1306 WriteLatencies.begin(), WriteLatencies.end()); in GenSchedClassTables()
1307 if (WLPos != SchedTables.WriteLatencies.end()) { in GenSchedClassTables()
1308 unsigned idx = WLPos - SchedTables.WriteLatencies.begin(); in GenSchedClassTables()
1310 for (unsigned i = 0, e = WriteLatencies.size(); i < e; ++i) in GenSchedClassTables()
1317 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size(); in GenSchedClassTables()
1318 llvm::append_range(SchedTables.WriteLatencies, WriteLatencies); in GenSchedClassTables()
1361 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size(); in EmitSchedClassTables()
1363 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx]; in EmitSchedClassTables()