Lines Matching refs:ModelDef
888 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindWriteResources() local
889 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
919 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
940 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindReadAdvance() local
941 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
971 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
1443 PrintFatalError(PM.ModelDef->getLoc(), "SchedMachineModel defines " in EmitProcessorModels()
1449 EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ','); in EmitProcessorModels()
1450 EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ','); in EmitProcessorModels()
1451 EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ','); in EmitProcessorModels()
1452 EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ','); in EmitProcessorModels()
1453 EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ','); in EmitProcessorModels()
1454 EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ','); in EmitProcessorModels()
1457 (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false); in EmitProcessorModels()
1463 (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false); in EmitProcessorModels()
1469 (PM.ModelDef ? PM.ModelDef->getValueAsBit("EnableIntervals") : false); in EmitProcessorModels()