Lines Matching refs:getName
121 << "extern const MCRegisterClass " << Target.getName() in runEnums()
129 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
164 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
180 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
228 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
369 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) in finalizeDwarfRegNumsKeys()
378 return A.first->getName() == B.first->getName(); in finalizeDwarfRegNumsKeys()
825 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
907 RegStrings.add(std::string(Reg.getName())); in runMCDesc()
944 const std::string &TargetName = std::string(Target.getName()); in runMCDesc()
969 << Idx.getName() << "\n"; in runMCDesc()
991 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " in runMCDesc()
1027 const std::string &Name = RC.getName(); in runMCDesc()
1061 std::string RCName = Order.empty() ? "nullptr" : RC.getName(); in runMCDesc()
1062 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits"; in runMCDesc()
1069 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1127 const std::string &TargetName = std::string(Target.getName()); in runTargetHeader()
1188 const std::string &Name = RC.getName(); in runTargetHeader()
1213 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1254 OS << Idx.getName(); in runTargetDesc()
1264 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1294 << RC.getName() << '\n'; in runTargetDesc()
1328 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1343 OS << "// " << Idx.getName(); in runTargetDesc()
1363 << RC.getName() << "Superclasses[] = {\n"; in runTargetDesc()
1372 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1375 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1386 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1395 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1406 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1407 << "RegClass = {\n " << '&' << Target.getName() in runTargetDesc()
1408 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " in runTargetDesc()
1409 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " in runTargetDesc()
1422 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1426 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1441 const std::string &TargetName = std::string(Target.getName()); in runTargetDesc()
1489 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; in runTargetDesc()
1514 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1517 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1518 << " -> " << SRC->getName() << "\n"; in runTargetDesc()
1520 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1547 OS << " {\t// " << RC.getName() << '\n'; in runTargetDesc()
1559 << RC.getName() << ':' << Idx.getName(); in runTargetDesc()
1563 OS << " -> " << SubRegClass->getName(); in runTargetDesc()
1620 << ", // " << Reg.getName() << "\n"; in runTargetDesc()
1683 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1711 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1723 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1738 if (Category.getName() == "GeneralPurposeRegisters") { in runTargetDesc()
1752 if (Category.getName() == "FixedRegisters") { in runTargetDesc()
1766 if (Category.getName() == "ArgumentRegisters") { in runTargetDesc()
1789 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1836 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1851 OS << " " << R->getName(); in debugDump()
1859 OS << " " << SRC.getName(); in debugDump()
1864 OS << " " << SRC->getName(); in debugDump()
1870 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1877 OS << "Register " << R.getName() << ":\n"; in debugDump()
1885 OS << "\tSubReg " << P.first->getName() in debugDump()
1886 << " = " << P.second->getName() << '\n'; in debugDump()