88   void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
91                             const std::deque<CodeGenRegister> &Regs,
219     const CodeGenRegister::Vec &Regs = RC.getMembers();  in EmitRegUnitPressure()  local
221     if (Regs.empty() || RC.Artificial)  in EmitRegUnitPressure()
384     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {  in EmitRegMappingTables()  argument
390   for (auto &RE : Regs) {  in EmitRegMappingTables()
406   StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");  in EmitRegMappingTables()
451   for (auto &RE : Regs) {  in EmitRegMappingTables()
511     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {  in EmitRegMapping()  argument
515   for (auto &RE : Regs) {  in EmitRegMapping()
524   StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace");  in EmitRegMapping()
878   const auto &Regs = RegBank.getRegisters();  in runMCDesc()  local
887   SmallVector<DiffVec, 4> SubRegLists(Regs.size());  in runMCDesc()
888   SmallVector<DiffVec, 4> SuperRegLists(Regs.size());  in runMCDesc()
889   SmallVector<DiffVec, 4> RegUnitLists(Regs.size());  in runMCDesc()
893   SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());  in runMCDesc()
899   SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());  in runMCDesc()
905   for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {  in runMCDesc()
984   for (const auto &Reg : Regs) {  in runMCDesc()
1077   EmitRegMappingTables(OS, Regs, false);  in runMCDesc()
1084   for (const auto &RE : Regs) {  in runMCDesc()
1102      << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "  in runMCDesc()
1111   EmitRegMapping(OS, Regs, false);  in runMCDesc()
1442   const auto &Regs = RegBank.getRegisters();  in runTargetDesc()  local
1444   for (const auto &Reg : Regs)  in runTargetDesc()
1448   llvm::BitVector InAllocClass(Regs.size() + 1, false);  in runTargetDesc()
1454   for (const auto &Reg : Regs) {  in runTargetDesc()
1607       OS << "  static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n";  in runTargetDesc()
1609       for (const CodeGenRegister &Reg : Regs) {  in runTargetDesc()
1644   EmitRegMappingTables(OS, Regs, true);  in runTargetDesc()
1656      << "  InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1  in runTargetDesc()
1670   EmitRegMapping(OS, Regs, true);  in runTargetDesc()
1679     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);  in runTargetDesc()  local
1680     assert(Regs && "Cannot expand CalleeSavedRegs instance");  in runTargetDesc()
1685     for (unsigned r = 0, re = Regs->size(); r != re; ++r)  in runTargetDesc()
1686       OS << getQualifiedName((*Regs)[r]) << ", ";  in runTargetDesc()
1690     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);  in runTargetDesc()
1778   for (const auto &Reg : Regs)  in runTargetDesc()