Lines Matching refs:OS
85 void debugDump(raw_ostream &OS);
93 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
97 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
104 void RegisterInfoEmitter::runEnums(raw_ostream &OS, in runEnums() argument
113 emitSourceFileHeader("Target Register Enum Values", OS); in runEnums()
115 OS << "\n#ifdef GET_REGINFO_ENUM\n"; in runEnums()
116 OS << "#undef GET_REGINFO_ENUM\n\n"; in runEnums()
118 OS << "namespace llvm {\n\n"; in runEnums()
120 OS << "class MCRegisterClass;\n" in runEnums()
125 OS << "namespace " << Namespace << " {\n"; in runEnums()
126 OS << "enum {\n NoRegister,\n"; in runEnums()
129 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; in runEnums()
132 OS << " NUM_TARGET_REGS // " << Registers.size()+1 << "\n"; in runEnums()
133 OS << "};\n"; in runEnums()
135 OS << "} // end namespace " << Namespace << "\n"; in runEnums()
144 OS << "\n// Register classes\n\n"; in runEnums()
146 OS << "namespace " << Namespace << " {\n"; in runEnums()
147 OS << "enum {\n"; in runEnums()
149 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; in runEnums()
150 OS << "\n};\n"; in runEnums()
152 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
159 OS << "\n// Register alternate name indices\n\n"; in runEnums()
161 OS << "namespace " << Namespace << " {\n"; in runEnums()
162 OS << "enum {\n"; in runEnums()
164 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; in runEnums()
165 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; in runEnums()
166 OS << "};\n"; in runEnums()
168 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
173 OS << "\n// Subregister indices\n\n"; in runEnums()
176 OS << "namespace " << Namespace << " {\n"; in runEnums()
177 OS << "enum : uint16_t {\n NoSubRegister,\n"; in runEnums()
180 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; in runEnums()
181 OS << " NUM_TARGET_SUBREGS\n};\n"; in runEnums()
183 OS << "} // end namespace " << Namespace << "\n\n"; in runEnums()
186 OS << "// Register pressure sets enum.\n"; in runEnums()
188 OS << "namespace " << Namespace << " {\n"; in runEnums()
189 OS << "enum RegisterPressureSets {\n"; in runEnums()
193 OS << " " << RegUnits.Name << " = " << i << ",\n"; in runEnums()
195 OS << "};\n"; in runEnums()
197 OS << "} // end namespace " << Namespace << '\n'; in runEnums()
198 OS << '\n'; in runEnums()
200 OS << "} // end namespace llvm\n\n"; in runEnums()
201 OS << "#endif // GET_REGINFO_ENUM\n\n"; in runEnums()
204 static void printInt(raw_ostream &OS, int Val) { in printInt() argument
205 OS << Val; in printInt()
209 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure() argument
214 OS << "/// Get the weight in units of pressure for this register class.\n" in EmitRegUnitPressure()
220 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
222 OS << '0'; in EmitRegUnitPressure()
226 OS << RegBank.getRegUnitSetWeight(RegUnits); in EmitRegUnitPressure()
228 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
230 OS << " };\n" in EmitRegUnitPressure()
242 OS << "/// Get the weight in units of pressure for this register unit.\n" in EmitRegUnitPressure()
248 OS << " static const uint8_t RUWeightTable[] = {\n "; in EmitRegUnitPressure()
253 OS << RU.Weight << ", "; in EmitRegUnitPressure()
255 OS << "};\n" in EmitRegUnitPressure()
259 OS << " // All register units have unit weight.\n" in EmitRegUnitPressure()
262 OS << "}\n\n"; in EmitRegUnitPressure()
264 OS << "\n" in EmitRegUnitPressure()
269 OS << "// Get the name of this register unit pressure set.\n" in EmitRegUnitPressure()
277 OS << " \"" << RegUnits.Name << "\",\n"; in EmitRegUnitPressure()
279 OS << " };\n" in EmitRegUnitPressure()
283 OS << "// Get the register unit pressure limit for this dimension.\n" in EmitRegUnitPressure()
292 OS << " " << RegUnits.Weight << ", \t// " << i << ": " in EmitRegUnitPressure()
295 OS << " };\n" in EmitRegUnitPressure()
318 OS << "/// Table of pressure sets per register class or unit.\n" in EmitRegUnitPressure()
320 PSetsSeqs.emit(OS, printInt, "-1"); in EmitRegUnitPressure()
321 OS << "};\n\n"; in EmitRegUnitPressure()
323 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
328 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
331 OS << PSetsSeqs.get(PSets[i]) << ","; in EmitRegUnitPressure()
333 OS << "};\n" in EmitRegUnitPressure()
337 OS << "/// Get the dimensions of register pressure impacted by this " in EmitRegUnitPressure()
344 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) in EmitRegUnitPressure()
348 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) in EmitRegUnitPressure()
351 OS << "};\n" in EmitRegUnitPressure()
384 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMappingTables() argument
408 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; in EmitRegMappingTables()
413 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
414 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
415 OS << I << "Dwarf2L[]"; in EmitRegMappingTables()
418 OS << " = {\n"; in EmitRegMappingTables()
431 OS << " { " << I.first << "U, " << getQualifiedName(I.second) in EmitRegMappingTables()
434 OS << "};\n"; in EmitRegMappingTables()
436 OS << ";\n"; in EmitRegMappingTables()
441 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
444 OS << " = std::size(" << Namespace in EmitRegMappingTables()
447 OS << ";\n\n"; in EmitRegMappingTables()
477 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; in EmitRegMappingTables()
478 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); in EmitRegMappingTables()
479 OS << i << "L2Dwarf[]"; in EmitRegMappingTables()
481 OS << " = {\n"; in EmitRegMappingTables()
489 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo in EmitRegMappingTables()
492 OS << "};\n"; in EmitRegMappingTables()
494 OS << ";\n"; in EmitRegMappingTables()
499 OS << "extern const unsigned " << Namespace in EmitRegMappingTables()
502 OS << " = std::size(" << Namespace in EmitRegMappingTables()
505 OS << ";\n\n"; in EmitRegMappingTables()
511 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { in EmitRegMapping() argument
528 OS << " switch ("; in EmitRegMapping()
530 OS << "DwarfFlavour"; in EmitRegMapping()
532 OS << "EHFlavour"; in EmitRegMapping()
533 OS << ") {\n" in EmitRegMapping()
538 OS << " case " << i << ":\n"; in EmitRegMapping()
539 OS << " "; in EmitRegMapping()
541 OS << "RI->"; in EmitRegMapping()
546 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
548 OS << "false"; in EmitRegMapping()
550 OS << "true"; in EmitRegMapping()
551 OS << ");\n"; in EmitRegMapping()
552 OS << " break;\n"; in EmitRegMapping()
554 OS << " }\n"; in EmitRegMapping()
559 OS << " switch ("; in EmitRegMapping()
561 OS << "DwarfFlavour"; in EmitRegMapping()
563 OS << "EHFlavour"; in EmitRegMapping()
564 OS << ") {\n" in EmitRegMapping()
569 OS << " case " << i << ":\n"; in EmitRegMapping()
570 OS << " "; in EmitRegMapping()
572 OS << "RI->"; in EmitRegMapping()
577 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; in EmitRegMapping()
579 OS << "false"; in EmitRegMapping()
581 OS << "true"; in EmitRegMapping()
582 OS << ");\n"; in EmitRegMapping()
583 OS << " break;\n"; in EmitRegMapping()
585 OS << " }\n"; in EmitRegMapping()
591 static void printBitVectorAsHex(raw_ostream &OS, in printBitVectorAsHex() argument
600 OS << format("0x%0*x, ", Digits, Value); in printBitVectorAsHex()
614 void print(raw_ostream &OS) { in print() argument
615 printBitVectorAsHex(OS, Values, 8); in print()
619 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { in printSimpleValueType() argument
620 OS << getEnumName(VT); in printSimpleValueType()
623 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { in printSubRegIndex() argument
624 OS << Idx->EnumValue; in printSubRegIndex()
666 static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; } in printDiff16() argument
668 static void printMask(raw_ostream &OS, LaneBitmask Val) { in printMask() argument
669 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; in printMask()
694 RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, in emitComposeSubRegIndices() argument
698 OS << "unsigned " << ClName in emitComposeSubRegIndices()
733 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) in emitComposeSubRegIndices()
736 OS << RowMap[i] << ", "; in emitComposeSubRegIndices()
737 OS << "\n };\n"; in emitComposeSubRegIndices()
741 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) in emitComposeSubRegIndices()
744 OS << " { "; in emitComposeSubRegIndices()
747 OS << Rows[r][i]->getQualifiedName() << ", "; in emitComposeSubRegIndices()
749 OS << "0, "; in emitComposeSubRegIndices()
750 OS << "},\n"; in emitComposeSubRegIndices()
752 OS << " };\n\n"; in emitComposeSubRegIndices()
754 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" in emitComposeSubRegIndices()
757 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; in emitComposeSubRegIndices()
759 OS << " return Rows[0][IdxB];\n"; in emitComposeSubRegIndices()
760 OS << "}\n\n"; in emitComposeSubRegIndices()
764 RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, in emitComposeSubRegIndexLaneMask() argument
795 OS << " struct MaskRolOp {\n" in emitComposeSubRegIndexLaneMask()
802 OS << " "; in emitComposeSubRegIndexLaneMask()
806 printMask(OS << "{ ", P.Mask); in emitComposeSubRegIndexLaneMask()
807 OS << format(", %2u }, ", P.RotateLeft); in emitComposeSubRegIndexLaneMask()
809 OS << "{ LaneBitmask::getNone(), 0 }"; in emitComposeSubRegIndexLaneMask()
811 OS << ", "; in emitComposeSubRegIndexLaneMask()
812 OS << " // Sequence " << Idx << "\n"; in emitComposeSubRegIndexLaneMask()
817 OS << " };\n" in emitComposeSubRegIndexLaneMask()
821 OS << " "; in emitComposeSubRegIndexLaneMask()
822 OS << SubReg2SequenceIndexMap[i]; in emitComposeSubRegIndexLaneMask()
824 OS << ","; in emitComposeSubRegIndexLaneMask()
825 OS << " // to " << SubRegIndices[i].getName() << "\n"; in emitComposeSubRegIndexLaneMask()
827 OS << " };\n\n"; in emitComposeSubRegIndexLaneMask()
829 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
847 OS << "LaneBitmask " << ClName in emitComposeSubRegIndexLaneMask()
871 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, in runMCDesc() argument
873 emitSourceFileHeader("MC Register Information", OS); in runMCDesc()
875 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; in runMCDesc()
876 OS << "#undef GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
942 OS << "namespace llvm {\n\n"; in runMCDesc()
947 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n"; in runMCDesc()
948 DiffSeqs.emit(OS, printDiff16); in runMCDesc()
949 OS << "};\n\n"; in runMCDesc()
952 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; in runMCDesc()
955 LaneMaskSeqs.emit(OS, printMask, "LaneBitmask::getAll()"); in runMCDesc()
956 OS << "};\n\n"; in runMCDesc()
959 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; in runMCDesc()
960 SubRegIdxSeqs.emit(OS, printSubRegIndex); in runMCDesc()
961 OS << "};\n\n"; in runMCDesc()
964 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runMCDesc()
966 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; in runMCDesc()
968 OS << " { " << Idx.Offset << ", " << Idx.Size << " },\t// " in runMCDesc()
971 OS << "};\n\n"; in runMCDesc()
975 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + in runMCDesc()
978 OS << "extern const MCRegisterDesc " << TargetName in runMCDesc()
980 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; in runMCDesc()
991 OS << " { " << RegStrings.get(std::string(Reg.getName())) << ", " in runMCDesc()
998 OS << "};\n\n"; // End of register descriptors... in runMCDesc()
1002 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; in runMCDesc()
1007 OS << " { "; in runMCDesc()
1010 OS << LS << getQualifiedName(R->TheDef); in runMCDesc()
1011 OS << " },\n"; in runMCDesc()
1013 OS << "};\n\n"; in runMCDesc()
1018 OS << "namespace { // Register classes...\n"; in runMCDesc()
1033 OS << " // " << Name << " Register Class...\n" in runMCDesc()
1036 OS << getQualifiedName(Reg) << ", "; in runMCDesc()
1038 OS << "\n };\n\n"; in runMCDesc()
1040 OS << " // " << Name << " Bit set.\n" in runMCDesc()
1046 BVE.print(OS); in runMCDesc()
1047 OS << "\n };\n\n"; in runMCDesc()
1050 OS << "} // end anonymous namespace\n\n"; in runMCDesc()
1054 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); in runMCDesc()
1056 OS << "extern const MCRegisterClass " << TargetName in runMCDesc()
1068 OS << " { " << RCName << ", " << RCBitsName << ", " in runMCDesc()
1075 OS << "};\n\n"; in runMCDesc()
1077 EmitRegMappingTables(OS, Regs, false); in runMCDesc()
1080 OS << "extern const uint16_t " << TargetName; in runMCDesc()
1081 OS << "RegEncodingTable[] = {\n"; in runMCDesc()
1083 OS << " 0,\n"; in runMCDesc()
1092 OS << " " << Value << ",\n"; in runMCDesc()
1094 OS << "};\n"; // End of HW encoding table in runMCDesc()
1097 OS << "static inline void Init" << TargetName in runMCDesc()
1111 EmitRegMapping(OS, Regs, false); in runMCDesc()
1113 OS << "}\n\n"; in runMCDesc()
1115 OS << "} // end namespace llvm\n\n"; in runMCDesc()
1116 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; in runMCDesc()
1120 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, in runTargetHeader() argument
1122 emitSourceFileHeader("Register Information Header Fragment", OS); in runTargetHeader()
1124 OS << "\n#ifdef GET_REGINFO_HEADER\n"; in runTargetHeader()
1125 OS << "#undef GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1130 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; in runTargetHeader()
1132 OS << "namespace llvm {\n\n"; in runTargetHeader()
1134 OS << "class " << TargetName << "FrameLowering;\n\n"; in runTargetHeader()
1136 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" in runTargetHeader()
1141 OS << " unsigned composeSubRegIndicesImpl" in runTargetHeader()
1152 OS << " const RegClassWeight &getRegClassWeight(" in runTargetHeader()
1178 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) const override;\n"; in runTargetHeader()
1181 OS << "};\n\n"; in runTargetHeader()
1184 OS << "namespace " << RegisterClasses.front().Namespace in runTargetHeader()
1191 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; in runTargetHeader()
1193 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; in runTargetHeader()
1195 OS << "} // end namespace llvm\n\n"; in runTargetHeader()
1196 OS << "#endif // GET_REGINFO_HEADER\n\n"; in runTargetHeader()
1203 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, in runTargetDesc() argument
1205 emitSourceFileHeader("Target Register and Register Classes Information", OS); in runTargetDesc()
1207 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; in runTargetDesc()
1208 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1210 OS << "namespace llvm {\n\n"; in runTargetDesc()
1213 OS << "extern const MCRegisterClass " << Target.getName() in runTargetDesc()
1246 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; in runTargetDesc()
1247 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); in runTargetDesc()
1248 OS << "};\n"; in runTargetDesc()
1251 OS << "\nstatic const char *SubRegIndexNameTable[] = { \""; in runTargetDesc()
1254 OS << Idx.getName(); in runTargetDesc()
1255 OS << "\", \""; in runTargetDesc()
1257 OS << "\" };\n\n"; in runTargetDesc()
1260 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " in runTargetDesc()
1263 printMask(OS << " ", Idx.LaneMask); in runTargetDesc()
1264 OS << ", // " << Idx.getName() << '\n'; in runTargetDesc()
1266 OS << " };\n\n"; in runTargetDesc()
1268 OS << "\n"; in runTargetDesc()
1272 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" in runTargetDesc()
1276 OS << " // Mode = " << M << " ("; in runTargetDesc()
1278 OS << "Default"; in runTargetDesc()
1280 OS << CGH.getMode(M).Name; in runTargetDesc()
1281 OS << ")\n"; in runTargetDesc()
1287 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " in runTargetDesc()
1293 OS << ", /*VTLists+*/" << VTSeqs.get(VTs) << " }, // " in runTargetDesc()
1297 OS << "};\n"; in runTargetDesc()
1300 OS << "\nstatic const TargetRegisterClass *const " in runTargetDesc()
1328 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1330 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1341 OS << "\n "; in runTargetDesc()
1342 printBitVectorAsHex(OS, MaskBV, 32); in runTargetDesc()
1343 OS << "// " << Idx.getName(); in runTargetDesc()
1346 OS << "\n};\n\n"; in runTargetDesc()
1349 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; in runTargetDesc()
1351 SuperRegIdxSeqs.emit(OS, printSubRegIndex); in runTargetDesc()
1352 OS << "};\n\n"; in runTargetDesc()
1362 OS << "static const TargetRegisterClass *const " in runTargetDesc()
1365 OS << " &" << Super->getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1366 OS << " nullptr\n};\n\n"; in runTargetDesc()
1372 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1380 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; in runTargetDesc()
1382 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); in runTargetDesc()
1383 OS << " };\n"; in runTargetDesc()
1386 OS << " const MCRegisterClass &MCR = " << Target.getName() in runTargetDesc()
1392 OS << "),\n ArrayRef<MCPhysReg>("; in runTargetDesc()
1394 OS << "),\n ArrayRef(AltOrder" << oi; in runTargetDesc()
1395 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1402 OS << "\nnamespace " << RegisterClasses.front().Namespace in runTargetDesc()
1406 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1411 printMask(OS, RC.LaneMask); in runTargetDesc()
1412 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1420 OS << "NullRegClasses,\n "; in runTargetDesc()
1422 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1424 OS << "nullptr\n"; in runTargetDesc()
1426 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1427 OS << " };\n\n"; in runTargetDesc()
1430 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; in runTargetDesc()
1433 OS << "\nnamespace {\n"; in runTargetDesc()
1434 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; in runTargetDesc()
1436 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1437 OS << " };\n"; in runTargetDesc()
1438 OS << "} // end anonymous namespace\n"; in runTargetDesc()
1468 OS << "\nstatic const uint8_t " in runTargetDesc()
1472 OS << AllRegCostPerUse[J] << ", "; in runTargetDesc()
1474 OS << "};\n\n"; in runTargetDesc()
1476 OS << "\nstatic const bool " in runTargetDesc()
1479 OS << (InAllocClass[I] ? "true" : "false") << ", "; in runTargetDesc()
1481 OS << "};\n\n"; in runTargetDesc()
1483 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName in runTargetDesc()
1485 OS << "CostPerUseTable, " << NumRegCosts << ", " in runTargetDesc()
1487 OS << "};\n\n"; // End of register descriptors... in runTargetDesc()
1495 emitComposeSubRegIndices(OS, RegBank, ClassName); in runTargetDesc()
1496 emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName); in runTargetDesc()
1501 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1507 OS << " static const uint8_t Table["; in runTargetDesc()
1509 OS << " static const uint16_t Table["; in runTargetDesc()
1512 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1514 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1517 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() in runTargetDesc()
1520 OS << " 0,\t// " << Idx.getName() << "\n"; in runTargetDesc()
1522 OS << " },\n"; in runTargetDesc()
1524 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1531 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1538 OS << " static const uint8_t Table["; in runTargetDesc()
1540 OS << " static const uint16_t Table["; in runTargetDesc()
1544 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; in runTargetDesc()
1547 OS << " {\t// " << RC.getName() << '\n'; in runTargetDesc()
1558 OS << " " << EnumValue << ",\t// " in runTargetDesc()
1563 OS << " -> " << SubRegClass->getName(); in runTargetDesc()
1566 OS << '\n'; in runTargetDesc()
1569 OS << " },\n"; in runTargetDesc()
1571 OS << " };\n assert(RC && \"Missing regclass\");\n" in runTargetDesc()
1578 EmitRegUnitPressure(OS, RegBank, ClassName); in runTargetDesc()
1601 OS << "\n// Register to base register class mapping\n\n"; in runTargetDesc()
1602 OS << "\n"; in runTargetDesc()
1603 OS << "const TargetRegisterClass *" << ClassName in runTargetDesc()
1606 OS << " static const uint16_t InvalidRegClassID = UINT16_MAX;\n\n"; in runTargetDesc()
1607 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n"; in runTargetDesc()
1608 OS << " InvalidRegClassID, // NoRegister\n"; in runTargetDesc()
1618 OS << " " in runTargetDesc()
1622 OS << " };\n\n" in runTargetDesc()
1633 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; in runTargetDesc()
1634 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n"; in runTargetDesc()
1635 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; in runTargetDesc()
1636 OS << "extern const char " << TargetName << "RegStrings[];\n"; in runTargetDesc()
1637 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; in runTargetDesc()
1638 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; in runTargetDesc()
1639 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; in runTargetDesc()
1640 OS << "extern const MCRegisterInfo::SubRegCoveredBits " in runTargetDesc()
1642 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; in runTargetDesc()
1644 EmitRegMappingTables(OS, Regs, true); in runTargetDesc()
1646 OS << ClassName << "::\n" in runTargetDesc()
1654 printMask(OS, RegBank.CoveringLanes); in runTargetDesc()
1655 OS << ", RegClassInfos, VTLists, HwMode) {\n" in runTargetDesc()
1670 EmitRegMapping(OS, Regs, true); in runTargetDesc()
1672 OS << "}\n\n"; in runTargetDesc()
1683 OS << "static const MCPhysReg " << CSRSet->getName() in runTargetDesc()
1686 OS << getQualifiedName((*Regs)[r]) << ", "; in runTargetDesc()
1687 OS << "0 };\n"; in runTargetDesc()
1711 OS << "static const uint32_t " << CSRSet->getName() in runTargetDesc()
1713 printBitVectorAsHex(OS, Covered, 32); in runTargetDesc()
1714 OS << "};\n"; in runTargetDesc()
1716 OS << "\n\n"; in runTargetDesc()
1718 OS << "ArrayRef<const uint32_t *> " << ClassName in runTargetDesc()
1721 OS << " static const uint32_t *const Masks[] = {\n"; in runTargetDesc()
1723 OS << " " << CSRSet->getName() << "_RegMask,\n"; in runTargetDesc()
1724 OS << " };\n"; in runTargetDesc()
1725 OS << " return ArrayRef(Masks);\n"; in runTargetDesc()
1727 OS << " return std::nullopt;\n"; in runTargetDesc()
1729 OS << "}\n\n"; in runTargetDesc()
1733 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1740 OS << " " << RC->getQualifiedName() in runTargetDesc()
1744 OS << " false;\n"; in runTargetDesc()
1745 OS << "}\n\n"; in runTargetDesc()
1747 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1754 OS << " " << RC->getQualifiedName() in runTargetDesc()
1758 OS << " false;\n"; in runTargetDesc()
1759 OS << "}\n\n"; in runTargetDesc()
1761 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1768 OS << " " << RC->getQualifiedName() in runTargetDesc()
1772 OS << " false;\n"; in runTargetDesc()
1773 OS << "}\n\n"; in runTargetDesc()
1775 OS << "bool " << ClassName << "::\n" in runTargetDesc()
1780 OS << " PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n"; in runTargetDesc()
1781 OS << " false;\n"; in runTargetDesc()
1782 OS << "}\n\n"; in runTargetDesc()
1784 OS << "ArrayRef<const char *> " << ClassName in runTargetDesc()
1787 OS << " static const char *Names[] = {\n"; in runTargetDesc()
1789 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; in runTargetDesc()
1790 OS << " };\n"; in runTargetDesc()
1791 OS << " return ArrayRef(Names);\n"; in runTargetDesc()
1793 OS << " return std::nullopt;\n"; in runTargetDesc()
1795 OS << "}\n\n"; in runTargetDesc()
1797 OS << "const " << TargetName << "FrameLowering *\n" << TargetName in runTargetDesc()
1803 OS << "} // end namespace llvm\n\n"; in runTargetDesc()
1804 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; in runTargetDesc()
1807 void RegisterInfoEmitter::run(raw_ostream &OS) { in run() argument
1810 runEnums(OS, Target, RegBank); in run()
1813 runMCDesc(OS, Target, RegBank); in run()
1816 runTargetHeader(OS, Target, RegBank); in run()
1819 runTargetDesc(OS, Target, RegBank); in run()
1825 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { in debugDump() argument
1836 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1837 OS << "\tSpillSize: {"; in debugDump()
1839 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
1840 OS << " }\n\tSpillAlignment: {"; in debugDump()
1842 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; in debugDump()
1843 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; in debugDump()
1844 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; in debugDump()
1845 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1846 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1847 OS << "\tAllocatable: " << RC.Allocatable << '\n'; in debugDump()
1848 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; in debugDump()
1849 OS << "\tRegs:"; in debugDump()
1851 OS << " " << R->getName(); in debugDump()
1853 OS << '\n'; in debugDump()
1854 OS << "\tSubClasses:"; in debugDump()
1859 OS << " " << SRC.getName(); in debugDump()
1861 OS << '\n'; in debugDump()
1862 OS << "\tSuperClasses:"; in debugDump()
1864 OS << " " << SRC->getName(); in debugDump()
1866 OS << '\n'; in debugDump()
1870 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1871 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1872 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
1873 OS << "\tOffset, Size: " << SRI.Offset << ", " << SRI.Size << '\n'; in debugDump()
1877 OS << "Register " << R.getName() << ":\n"; in debugDump()
1878 OS << "\tCostPerUse: "; in debugDump()
1880 OS << Cost << " "; in debugDump()
1881 OS << '\n'; in debugDump()
1882 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; in debugDump()
1883 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; in debugDump()
1885 OS << "\tSubReg " << P.first->getName() in debugDump()