Lines Matching refs:CodeGenRegBank
64 CodeGenRegBank &RegBank = Target.getRegBank(); in RegisterInfoEmitter()
69 void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
72 void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
76 CodeGenRegBank &Bank);
80 CodeGenRegBank &Bank);
93 void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
95 void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
97 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
105 CodeGenTarget &Target, CodeGenRegBank &Bank) { in runEnums()
209 EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, in EmitRegUnitPressure()
695 CodeGenRegBank &RegBank, in emitComposeSubRegIndices()
765 CodeGenRegBank &RegBank, in emitComposeSubRegIndexLaneMask()
872 CodeGenRegBank &RegBank) { in runMCDesc()
1121 CodeGenRegBank &RegBank) { in runTargetHeader()
1204 CodeGenRegBank &RegBank){ in runTargetDesc()
1808 CodeGenRegBank &RegBank = Target.getRegBank(); in run()
1826 CodeGenRegBank &RegBank = Target.getRegBank(); in debugDump()