Lines Matching refs:InstRWs
956 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; in collectSchedClasses()
1090 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; in createInstRWClass()
1120 SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef); in createInstRWClass()
1140 for (Record *OldRWDef : SchedClasses[OldSCIdx].InstRWs) { in createInstRWClass()
1153 SC.InstRWs.push_back(OldRWDef); in createInstRWClass()
1159 SC.InstRWs.push_back(InstRWDef); in createInstRWClass()
1254 if (!SchedClasses[Idx].InstRWs.empty()) in inferSchedClasses()
1290 for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) { in inferFromInstRWs()
1291 assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!"); in inferFromInstRWs()
1292 Record *Rec = SchedClasses[SCIdx].InstRWs[I]; in inferFromInstRWs()
1914 for (Record *RW : SC.InstRWs) { in collectProcResources()
2029 const RecVec &InstRWs = SC.InstRWs; in checkCompleteness() local
2030 auto I = find_if(InstRWs, [&ProcModel](const Record *R) { in checkCompleteness()
2033 if (I == InstRWs.end()) { in checkCompleteness()