617       IsWrite((Packed >> kIsWriteShift) & kIsWriteMask),  in ASanAccessInfo()
620 ASanAccessInfo::ASanAccessInfo(bool IsWrite, bool CompileKernel,  in ASanAccessInfo()  argument
622     : Packed((IsWrite << kIsWriteShift) +  in ASanAccessInfo()
625       AccessSizeIndex(AccessSizeIndex), IsWrite(IsWrite),  in ASanAccessInfo()
698                          uint32_t TypeStoreSize, bool IsWrite,
702                                        uint32_t TypeStoreSize, bool IsWrite,
708                                         TypeSize TypeStoreSize, bool IsWrite,
715                                    Type *OpType, bool IsWrite,
721                                  bool IsWrite, size_t AccessSizeIndex,
1357       bool IsWrite = CI->getType()->isVoidTy();  in getInterestingMemoryOperands()  local
1359       unsigned OpOffset = IsWrite ? 1 : 0;  in getInterestingMemoryOperands()
1360       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1366       Type *Ty = IsWrite ? CI->getArgOperand(0)->getType() : CI->getType();  in getInterestingMemoryOperands()
1372       Interesting.emplace_back(I, OpOffset, IsWrite, Ty, Alignment, Mask);  in getInterestingMemoryOperands()
1377       bool IsWrite = CI->getIntrinsicID() == Intrinsic::masked_compressstore;  in getInterestingMemoryOperands()  local
1378       unsigned OpOffset = IsWrite ? 1 : 0;  in getInterestingMemoryOperands()
1379       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1385       Type *Ty = IsWrite ? CI->getArgOperand(0)->getType() : CI->getType();  in getInterestingMemoryOperands()
1394       Interesting.emplace_back(I, OpOffset, IsWrite, Ty, Alignment, TrueMask,  in getInterestingMemoryOperands()
1404       bool IsWrite = CI->getType()->isVoidTy();  in getInterestingMemoryOperands()  local
1405       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1408       Type *Ty = IsWrite ? CI->getArgOperand(0)->getType() : CI->getType();  in getInterestingMemoryOperands()
1422       Interesting.emplace_back(I, PtrOpNo, IsWrite, Ty, Alignment,  in getInterestingMemoryOperands()
1431       bool IsWrite = IID == Intrinsic::vp_scatter;  in getInterestingMemoryOperands()  local
1432       if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads)  in getInterestingMemoryOperands()
1435       Type *Ty = IsWrite ? CI->getArgOperand(0)->getType() : CI->getType();  in getInterestingMemoryOperands()
1437       Interesting.emplace_back(I, PtrOpNo, IsWrite, Ty, Alignment,  in getInterestingMemoryOperands()
1514                                 TypeSize TypeStoreSize, bool IsWrite,  in doInstrumentAddress()  argument
1530                                        FixedSize, IsWrite, nullptr, UseCalls,  in doInstrumentAddress()
1535                                          IsWrite, nullptr, UseCalls, Exp);  in doInstrumentAddress()
1541     MaybeAlign Alignment, unsigned Granularity, Type *OpType, bool IsWrite,  in instrumentMaskedLoadOrStore()  argument
1599                         ElemTypeSize, IsWrite, SizeArgument, UseCalls, Exp);  in instrumentMaskedLoadOrStore()
1641   if (O.IsWrite)  in instrumentMop()
1650                                 Granularity, O.OpType, O.IsWrite, nullptr,  in instrumentMop()
1654                         Granularity, O.TypeStoreSize, O.IsWrite, nullptr, UseCalls,  in instrumentMop()
1660                                                  Value *Addr, bool IsWrite,  in generateCrashCode()  argument
1669       Call = IRB.CreateCall(AsanErrorCallbackSized[IsWrite][0],  in generateCrashCode()
1672       Call = IRB.CreateCall(AsanErrorCallbackSized[IsWrite][1],  in generateCrashCode()
1677           IRB.CreateCall(AsanErrorCallback[IsWrite][0][AccessSizeIndex], Addr);  in generateCrashCode()
1679       Call = IRB.CreateCall(AsanErrorCallback[IsWrite][1][AccessSizeIndex],  in generateCrashCode()
1707     uint32_t TypeStoreSize, bool IsWrite, Value *SizeArgument) {  in instrumentAMDGPUAddress()  argument
1754                                          uint32_t TypeStoreSize, bool IsWrite,  in instrumentAddress()  argument
1759                                            TypeStoreSize, IsWrite, SizeArgument);  in instrumentAddress()
1766   const ASanAccessInfo AccessInfo(IsWrite, CompileKernel, AccessSizeIndex);  in instrumentAddress()
1769     const ASanAccessInfo AccessInfo(IsWrite, CompileKernel, AccessSizeIndex);  in instrumentAddress()
1781       IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][0][AccessSizeIndex],  in instrumentAddress()
1784       IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][1][AccessSizeIndex],  in instrumentAddress()
1832   Instruction *Crash = generateCrashCode(CrashTerm, AddrLong, IsWrite,  in instrumentAddress()
1844     bool IsWrite, Value *SizeArgument, bool UseCalls, uint32_t Exp) {  in instrumentUnusualSizeOrAlignment()  argument
1852       IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][0],  in instrumentUnusualSizeOrAlignment()
1855       IRB.CreateCall(AsanMemoryAccessCallbackSized[IsWrite][1],  in instrumentUnusualSizeOrAlignment()
1862     instrumentAddress(I, InsertBefore, Addr, {}, 8, IsWrite, Size, false, Exp);  in instrumentUnusualSizeOrAlignment()
1863     instrumentAddress(I, InsertBefore, LastByte, {}, 8, IsWrite, Size, false,  in instrumentUnusualSizeOrAlignment()