Lines Matching refs:BasePtr
70 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
75 BasePtr = X86::ESI; in X86RegisterInfo()
571 Register BasePtr = getX86SubSuperRegister(getBaseRegister(), 64); in getReservedRegs() local
572 for (const MCPhysReg &SubReg : subregs_inclusive(BasePtr)) in getReservedRegs()
788 return MRI->canReserveReg(BasePtr); in canRealignStack()
813 Register BasePtr = MI.getOperand(1).getReg(); in tryOptimizeLEAtoMOV() local
818 BasePtr = getX86SubSuperRegister(BasePtr, 32); in tryOptimizeLEAtoMOV()
822 TII->copyPhysReg(*MI.getParent(), II, MI.getDebugLoc(), NewDestReg, BasePtr, in tryOptimizeLEAtoMOV()
856 assert(BasePtr == FramePtr && "Expected the FP as base register"); in eliminateFrameIndex()
893 Register BasePtr; in eliminateFrameIndex() local
899 TFI->getFrameIndexReferenceSP(MF, FrameIndex, BasePtr, 0).getFixed(); in eliminateFrameIndex()
901 FIOffset = TFI->getWin64EHFrameIndexRef(MF, FrameIndex, BasePtr); in eliminateFrameIndex()
903 FIOffset = TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed(); in eliminateFrameIndex()
922 Register MachineBasePtr = BasePtr; in eliminateFrameIndex()
923 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr)) in eliminateFrameIndex()
924 MachineBasePtr = getX86SubSuperRegister(BasePtr, 64); in eliminateFrameIndex()
930 if (BasePtr == StackPtr) in eliminateFrameIndex()
936 assert(BasePtr == FramePtr && "Expected the FP as base register"); in eliminateFrameIndex()