Lines Matching refs:AddrIndexReg
478 MI.getOperand(Op + X86::AddrIndexReg).isReg() && in isFrameOperand()
481 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 && in isFrameOperand()
908 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
909 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
928 MI.getOperand(1 + X86::AddrIndexReg).isReg() && in isReallyTriviallyReMaterializable()
929 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 && in isReallyTriviallyReMaterializable()
3505 const MachineOperand &Index = MI.getOperand(OpNo + X86::AddrIndexReg); in getConstantFromPool()
4404 AM.ScaledReg = MemI.getOperand(MemRefBegin + X86::AddrIndexReg).getReg(); in getAddrModeFromMemoryOp()
4528 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() != in getMemOperandsWithOffsetWidth()
4594 MachineOperand &MO = NewMI->getOperand(X86::AddrIndexReg); in loadStoreTileReg()
4607 MachineOperand &MO = NewMI->getOperand(1 + X86::AddrIndexReg); in loadStoreTileReg()
8681 !HasSameOp(X86::AddrIndexReg) || !HasSameOp(X86::AddrSegmentReg)) in areLoadsFromSameBasePtr()