407   Register DestReg = I->getOperand(0).getReg();  in searchALUInst()  local
419         if (Opnd.getReg() == DestReg) {  in searchALUInst()
440         if (TRI->regsOverlap(DestReg, Opnd.getReg()))  in searchALUInst()
565   Register DestReg = MI.getOperand(0).getReg();  in optTwoAddrLEA()  local
570   if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))  in optTwoAddrLEA()
587       (DestReg == BaseReg || DestReg == IndexReg)) {  in optTwoAddrLEA()
589     if (DestReg != BaseReg)  in optTwoAddrLEA()
594       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
599       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
602   } else if (DestReg == BaseReg && IndexReg == 0) {  in optTwoAddrLEA()
616         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
619         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
626         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
630         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)  in optTwoAddrLEA()
758   Register DestReg = Dest.getReg();  in processInstrForSlow3OpLEA()  local
775   if (IsInefficientBase && DestReg == BaseReg && !IsScale1)  in processInstrForSlow3OpLEA()
782   bool BaseOrIndexIsDst = DestReg == BaseReg || DestReg == IndexReg;  in processInstrForSlow3OpLEA()
811     if (DestReg != BaseReg)  in processInstrForSlow3OpLEA()
816       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
822       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
850         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
851                     .addReg(DestReg);  in processInstrForSlow3OpLEA()
855         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
856                     .addReg(DestReg)  in processInstrForSlow3OpLEA()
869   assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");  in processInstrForSlow3OpLEA()
879     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);  in processInstrForSlow3OpLEA()
883     NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
884                 .addReg(DestReg)  in processInstrForSlow3OpLEA()
906   NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)  in processInstrForSlow3OpLEA()
907               .addReg(DestReg)  in processInstrForSlow3OpLEA()