458   Register BaseReg = LeaI->getOperand(1 + X86::AddrBaseReg).getReg();  in checkRegUsage()  local
469       if (TRI->regsOverlap(Reg, BaseReg)) {  in checkRegUsage()
507   Register BaseReg = I->getOperand(1 + X86::AddrBaseReg).getReg();  in optLEAALU()  local
510     BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in optLEAALU()
514     if (BaseReg == IndexReg)  in optLEAALU()
516     std::swap(BaseReg, IndexReg);  in optLEAALU()
519   if (BaseReg == IndexReg)  in optLEAALU()
528                .addReg(BaseReg, KilledBase ? RegState::Kill : 0);  in optLEAALU()
566   Register BaseReg = Base.getReg();  in optTwoAddrLEA()  local
575     if (BaseReg != 0)  in optTwoAddrLEA()
576       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in optTwoAddrLEA()
586   if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&  in optTwoAddrLEA()
587       (DestReg == BaseReg || DestReg == IndexReg)) {  in optTwoAddrLEA()
589     if (DestReg != BaseReg)  in optTwoAddrLEA()
590       std::swap(BaseReg, IndexReg);  in optTwoAddrLEA()
595         .addReg(BaseReg).addReg(IndexReg)  in optTwoAddrLEA()
600         .addReg(BaseReg).addReg(IndexReg);  in optTwoAddrLEA()
602   } else if (DestReg == BaseReg && IndexReg == 0) {  in optTwoAddrLEA()
617           .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);  in optTwoAddrLEA()
620           .addReg(BaseReg);  in optTwoAddrLEA()
627           .addReg(BaseReg).addImm(Disp.getImm())  in optTwoAddrLEA()
631           .addReg(BaseReg).addImm(Disp.getImm());  in optTwoAddrLEA()
634   } else if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0) {  in optTwoAddrLEA()
759   Register BaseReg = Base.getReg();  in processInstrForSlow3OpLEA()  local
763     if (BaseReg != 0)  in processInstrForSlow3OpLEA()
764       BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);  in processInstrForSlow3OpLEA()
770   bool IsInefficientBase = isInefficientLEAReg(BaseReg);  in processInstrForSlow3OpLEA()
775   if (IsInefficientBase && DestReg == BaseReg && !IsScale1)  in processInstrForSlow3OpLEA()
782   bool BaseOrIndexIsDst = DestReg == BaseReg || DestReg == IndexReg;  in processInstrForSlow3OpLEA()
789   if (IsScale1 && BaseReg == IndexReg &&  in processInstrForSlow3OpLEA()
811     if (DestReg != BaseReg)  in processInstrForSlow3OpLEA()
812       std::swap(BaseReg, IndexReg);  in processInstrForSlow3OpLEA()
817                   .addReg(BaseReg)  in processInstrForSlow3OpLEA()
823                   .addReg(BaseReg)  in processInstrForSlow3OpLEA()
869   assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");  in processInstrForSlow3OpLEA()
878     bool BIK = Base.isKill() && BaseReg != IndexReg;  in processInstrForSlow3OpLEA()
879     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);  in processInstrForSlow3OpLEA()