Lines Matching refs:X86
161 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
219 X86::AddrIndexReg); in addFullAddress()
225 bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I, in foldX86XALUIntrinsic()
245 X86::CondCode TmpCC; in foldX86XALUIntrinsic()
251 case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break; in foldX86XALUIntrinsic()
253 case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break; in foldX86XALUIntrinsic()
337 Opc = X86::MOV8rm; in X86FastEmitLoad()
340 Opc = X86::MOV16rm; in X86FastEmitLoad()
343 Opc = X86::MOV32rm; in X86FastEmitLoad()
347 Opc = X86::MOV64rm; in X86FastEmitLoad()
350 Opc = HasAVX512 ? X86::VMOVSSZrm_alt in X86FastEmitLoad()
351 : HasAVX ? X86::VMOVSSrm_alt in X86FastEmitLoad()
352 : HasSSE1 ? X86::MOVSSrm_alt in X86FastEmitLoad()
353 : X86::LD_Fp32m; in X86FastEmitLoad()
356 Opc = HasAVX512 ? X86::VMOVSDZrm_alt in X86FastEmitLoad()
357 : HasAVX ? X86::VMOVSDrm_alt in X86FastEmitLoad()
358 : HasSSE2 ? X86::MOVSDrm_alt in X86FastEmitLoad()
359 : X86::LD_Fp64m; in X86FastEmitLoad()
366 Opc = HasVLX ? X86::VMOVNTDQAZ128rm : in X86FastEmitLoad()
367 HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm; in X86FastEmitLoad()
369 Opc = HasVLX ? X86::VMOVAPSZ128rm : in X86FastEmitLoad()
370 HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm; in X86FastEmitLoad()
372 Opc = HasVLX ? X86::VMOVUPSZ128rm : in X86FastEmitLoad()
373 HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm; in X86FastEmitLoad()
377 Opc = HasVLX ? X86::VMOVNTDQAZ128rm : in X86FastEmitLoad()
378 HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm; in X86FastEmitLoad()
380 Opc = HasVLX ? X86::VMOVAPDZ128rm : in X86FastEmitLoad()
381 HasAVX ? X86::VMOVAPDrm : X86::MOVAPDrm; in X86FastEmitLoad()
383 Opc = HasVLX ? X86::VMOVUPDZ128rm : in X86FastEmitLoad()
384 HasAVX ? X86::VMOVUPDrm : X86::MOVUPDrm; in X86FastEmitLoad()
391 Opc = HasVLX ? X86::VMOVNTDQAZ128rm : in X86FastEmitLoad()
392 HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm; in X86FastEmitLoad()
394 Opc = HasVLX ? X86::VMOVDQA64Z128rm : in X86FastEmitLoad()
395 HasAVX ? X86::VMOVDQArm : X86::MOVDQArm; in X86FastEmitLoad()
397 Opc = HasVLX ? X86::VMOVDQU64Z128rm : in X86FastEmitLoad()
398 HasAVX ? X86::VMOVDQUrm : X86::MOVDQUrm; in X86FastEmitLoad()
403 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; in X86FastEmitLoad()
407 Opc = HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm; in X86FastEmitLoad()
409 Opc = HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm; in X86FastEmitLoad()
414 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; in X86FastEmitLoad()
418 Opc = HasVLX ? X86::VMOVAPDZ256rm : X86::VMOVAPDYrm; in X86FastEmitLoad()
420 Opc = HasVLX ? X86::VMOVUPDZ256rm : X86::VMOVUPDYrm; in X86FastEmitLoad()
428 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; in X86FastEmitLoad()
432 Opc = HasVLX ? X86::VMOVDQA64Z256rm : X86::VMOVDQAYrm; in X86FastEmitLoad()
434 Opc = HasVLX ? X86::VMOVDQU64Z256rm : X86::VMOVDQUYrm; in X86FastEmitLoad()
439 Opc = X86::VMOVNTDQAZrm; in X86FastEmitLoad()
441 Opc = (Alignment >= 64) ? X86::VMOVAPSZrm : X86::VMOVUPSZrm; in X86FastEmitLoad()
446 Opc = X86::VMOVNTDQAZrm; in X86FastEmitLoad()
448 Opc = (Alignment >= 64) ? X86::VMOVAPDZrm : X86::VMOVUPDZrm; in X86FastEmitLoad()
458 Opc = X86::VMOVNTDQAZrm; in X86FastEmitLoad()
460 Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm; in X86FastEmitLoad()
496 Register AndResult = createResultReg(&X86::GR8RegClass); in X86FastEmitStore()
498 TII.get(X86::AND8ri), AndResult) in X86FastEmitStore()
503 case MVT::i8: Opc = X86::MOV8mr; break; in X86FastEmitStore()
504 case MVT::i16: Opc = X86::MOV16mr; break; in X86FastEmitStore()
506 Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTImr : X86::MOV32mr; in X86FastEmitStore()
510 Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTI_64mr : X86::MOV64mr; in X86FastEmitStore()
515 Opc = X86::MOVNTSS; in X86FastEmitStore()
517 Opc = HasAVX512 ? X86::VMOVSSZmr : in X86FastEmitStore()
518 HasAVX ? X86::VMOVSSmr : X86::MOVSSmr; in X86FastEmitStore()
520 Opc = X86::ST_Fp32m; in X86FastEmitStore()
525 Opc = X86::MOVNTSD; in X86FastEmitStore()
527 Opc = HasAVX512 ? X86::VMOVSDZmr : in X86FastEmitStore()
528 HasAVX ? X86::VMOVSDmr : X86::MOVSDmr; in X86FastEmitStore()
530 Opc = X86::ST_Fp64m; in X86FastEmitStore()
533 Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr; in X86FastEmitStore()
538 Opc = HasVLX ? X86::VMOVNTPSZ128mr : in X86FastEmitStore()
539 HasAVX ? X86::VMOVNTPSmr : X86::MOVNTPSmr; in X86FastEmitStore()
541 Opc = HasVLX ? X86::VMOVAPSZ128mr : in X86FastEmitStore()
542 HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr; in X86FastEmitStore()
544 Opc = HasVLX ? X86::VMOVUPSZ128mr : in X86FastEmitStore()
545 HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr; in X86FastEmitStore()
550 Opc = HasVLX ? X86::VMOVNTPDZ128mr : in X86FastEmitStore()
551 HasAVX ? X86::VMOVNTPDmr : X86::MOVNTPDmr; in X86FastEmitStore()
553 Opc = HasVLX ? X86::VMOVAPDZ128mr : in X86FastEmitStore()
554 HasAVX ? X86::VMOVAPDmr : X86::MOVAPDmr; in X86FastEmitStore()
556 Opc = HasVLX ? X86::VMOVUPDZ128mr : in X86FastEmitStore()
557 HasAVX ? X86::VMOVUPDmr : X86::MOVUPDmr; in X86FastEmitStore()
565 Opc = HasVLX ? X86::VMOVNTDQZ128mr : in X86FastEmitStore()
566 HasAVX ? X86::VMOVNTDQmr : X86::MOVNTDQmr; in X86FastEmitStore()
568 Opc = HasVLX ? X86::VMOVDQA64Z128mr : in X86FastEmitStore()
569 HasAVX ? X86::VMOVDQAmr : X86::MOVDQAmr; in X86FastEmitStore()
571 Opc = HasVLX ? X86::VMOVDQU64Z128mr : in X86FastEmitStore()
572 HasAVX ? X86::VMOVDQUmr : X86::MOVDQUmr; in X86FastEmitStore()
578 Opc = HasVLX ? X86::VMOVNTPSZ256mr : X86::VMOVNTPSYmr; in X86FastEmitStore()
580 Opc = HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr; in X86FastEmitStore()
582 Opc = HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr; in X86FastEmitStore()
588 Opc = HasVLX ? X86::VMOVNTPDZ256mr : X86::VMOVNTPDYmr; in X86FastEmitStore()
590 Opc = HasVLX ? X86::VMOVAPDZ256mr : X86::VMOVAPDYmr; in X86FastEmitStore()
592 Opc = HasVLX ? X86::VMOVUPDZ256mr : X86::VMOVUPDYmr; in X86FastEmitStore()
601 Opc = HasVLX ? X86::VMOVNTDQZ256mr : X86::VMOVNTDQYmr; in X86FastEmitStore()
603 Opc = HasVLX ? X86::VMOVDQA64Z256mr : X86::VMOVDQAYmr; in X86FastEmitStore()
605 Opc = HasVLX ? X86::VMOVDQU64Z256mr : X86::VMOVDQUYmr; in X86FastEmitStore()
610 Opc = IsNonTemporal ? X86::VMOVNTPSZmr : X86::VMOVAPSZmr; in X86FastEmitStore()
612 Opc = X86::VMOVUPSZmr; in X86FastEmitStore()
617 Opc = IsNonTemporal ? X86::VMOVNTPDZmr : X86::VMOVAPDZmr; in X86FastEmitStore()
619 Opc = X86::VMOVUPDZmr; in X86FastEmitStore()
629 Opc = IsNonTemporal ? X86::VMOVNTDQZmr : X86::VMOVDQA64Zmr; in X86FastEmitStore()
631 Opc = X86::VMOVDQU64Zmr; in X86FastEmitStore()
668 case MVT::i8: Opc = X86::MOV8mi; break; in X86FastEmitStore()
669 case MVT::i16: Opc = X86::MOV16mi; break; in X86FastEmitStore()
670 case MVT::i32: Opc = X86::MOV32mi; break; in X86FastEmitStore()
674 Opc = X86::MOV64mi32; in X86FastEmitStore()
754 AM.Base.Reg = X86::RIP; in handleConstantAddresses()
779 Opc = X86::MOV64rm; in handleConstantAddresses()
780 RC = &X86::GR64RegClass; in handleConstantAddresses()
782 Opc = X86::MOV32rm; in handleConstantAddresses()
783 RC = &X86::GR32RegClass; in handleConstantAddresses()
788 StubAM.Base.Reg = X86::RIP; in handleConstantAddresses()
1076 AM.Base.Reg = X86::RIP; in X86SelectCallAddress()
1091 Register CopyReg = createResultReg(&X86::GR32RegClass); in X86SelectCallAddress()
1092 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::MOV32rr), in X86SelectCallAddress()
1096 Register ExtReg = createResultReg(&X86::GR64RegClass); in X86SelectCallAddress()
1101 .addImm(X86::sub_32bit); in X86SelectCallAddress()
1239 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) in X86SelectRet()
1293 unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; in X86SelectRet()
1303 TII.get(Subtarget->is64Bit() ? X86::RETI64 : X86::RETI32)) in X86SelectRet()
1307 TII.get(Subtarget->is64Bit() ? X86::RET64 : X86::RET32)); in X86SelectRet()
1365 case MVT::i8: return X86::CMP8rr; in X86ChooseCmpOpcode()
1366 case MVT::i16: return X86::CMP16rr; in X86ChooseCmpOpcode()
1367 case MVT::i32: return X86::CMP32rr; in X86ChooseCmpOpcode()
1368 case MVT::i64: return X86::CMP64rr; in X86ChooseCmpOpcode()
1370 return HasAVX512 ? X86::VUCOMISSZrr in X86ChooseCmpOpcode()
1371 : HasAVX ? X86::VUCOMISSrr in X86ChooseCmpOpcode()
1372 : HasSSE1 ? X86::UCOMISSrr in X86ChooseCmpOpcode()
1375 return HasAVX512 ? X86::VUCOMISDZrr in X86ChooseCmpOpcode()
1376 : HasAVX ? X86::VUCOMISDrr in X86ChooseCmpOpcode()
1377 : HasSSE2 ? X86::UCOMISDrr in X86ChooseCmpOpcode()
1390 return X86::CMP8ri; in X86ChooseCmpImmediateOpcode()
1392 return X86::CMP16ri; in X86ChooseCmpImmediateOpcode()
1394 return X86::CMP32ri; in X86ChooseCmpImmediateOpcode()
1398 return isInt<32>(RHSC->getSExtValue()) ? X86::CMP64ri32 : 0; in X86ChooseCmpImmediateOpcode()
1452 ResultReg = createResultReg(&X86::GR32RegClass); in X86SelectCmp()
1453 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::MOV32r0), in X86SelectCmp()
1455 ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg, X86::sub_8bit); in X86SelectCmp()
1461 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectCmp()
1462 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::MOV8ri), in X86SelectCmp()
1487 { X86::COND_E, X86::COND_NP, X86::AND8rr }, in X86SelectCmp()
1488 { X86::COND_NE, X86::COND_P, X86::OR8rr } in X86SelectCmp()
1497 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectCmp()
1502 Register FlagReg1 = createResultReg(&X86::GR8RegClass); in X86SelectCmp()
1503 Register FlagReg2 = createResultReg(&X86::GR8RegClass); in X86SelectCmp()
1504 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr), in X86SelectCmp()
1506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr), in X86SelectCmp()
1514 X86::CondCode CC; in X86SelectCmp()
1516 std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate); in X86SelectCmp()
1517 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code."); in X86SelectCmp()
1526 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr), in X86SelectCmp()
1557 case MVT::i8: MovInst = X86::MOVZX32rr8; break; in X86SelectZExt()
1558 case MVT::i16: MovInst = X86::MOVZX32rr16; break; in X86SelectZExt()
1559 case MVT::i32: MovInst = X86::MOV32rr; break; in X86SelectZExt()
1563 Register Result32 = createResultReg(&X86::GR32RegClass); in X86SelectZExt()
1567 ResultReg = createResultReg(&X86::GR64RegClass); in X86SelectZExt()
1570 .addImm(0).addReg(Result32).addImm(X86::sub_32bit); in X86SelectZExt()
1574 Register Result32 = createResultReg(&X86::GR32RegClass); in X86SelectZExt()
1575 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::MOVZX32rr8), in X86SelectZExt()
1578 ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, X86::sub_16bit); in X86SelectZExt()
1608 ResultReg = createResultReg(&X86::GR8RegClass); in X86SelectSExt()
1609 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::NEG8r), in X86SelectSExt()
1618 Register Result32 = createResultReg(&X86::GR32RegClass); in X86SelectSExt()
1619 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::MOVSX32rr8), in X86SelectSExt()
1622 ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, X86::sub_16bit); in X86SelectSExt()
1644 X86::CondCode CC; in X86SelectBranch()
1694 std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate); in X86SelectBranch()
1695 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code."); in X86SelectBranch()
1704 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::JCC_1)) in X86SelectBranch()
1710 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::JCC_1)) in X86SelectBranch()
1711 .addMBB(TrueMBB).addImm(X86::COND_P); in X86SelectBranch()
1726 case MVT::i8: TestOpc = X86::TEST8ri; break; in X86SelectBranch()
1727 case MVT::i16: TestOpc = X86::TEST16ri; break; in X86SelectBranch()
1728 case MVT::i32: TestOpc = X86::TEST32ri; break; in X86SelectBranch()
1729 case MVT::i64: TestOpc = X86::TEST64ri32; break; in X86SelectBranch()
1738 unsigned JmpCond = X86::COND_NE; in X86SelectBranch()
1741 JmpCond = X86::COND_E; in X86SelectBranch()
1744 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::JCC_1)) in X86SelectBranch()
1758 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::JCC_1)) in X86SelectBranch()
1771 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { in X86SelectBranch()
1773 OpReg = createResultReg(&X86::GR32RegClass); in X86SelectBranch()
1777 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, X86::sub_8bit); in X86SelectBranch()
1779 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::TEST8ri)) in X86SelectBranch()
1782 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::JCC_1)) in X86SelectBranch()
1783 .addMBB(TrueMBB).addImm(X86::COND_NE); in X86SelectBranch()
1792 CReg = X86::CL; in X86SelectShift()
1793 RC = &X86::GR8RegClass; in X86SelectShift()
1795 case Instruction::LShr: OpReg = X86::SHR8rCL; break; in X86SelectShift()
1796 case Instruction::AShr: OpReg = X86::SAR8rCL; break; in X86SelectShift()
1797 case Instruction::Shl: OpReg = X86::SHL8rCL; break; in X86SelectShift()
1801 CReg = X86::CX; in X86SelectShift()
1802 RC = &X86::GR16RegClass; in X86SelectShift()
1805 case Instruction::LShr: OpReg = X86::SHR16rCL; break; in X86SelectShift()
1806 case Instruction::AShr: OpReg = X86::SAR16rCL; break; in X86SelectShift()
1807 case Instruction::Shl: OpReg = X86::SHL16rCL; break; in X86SelectShift()
1810 CReg = X86::ECX; in X86SelectShift()
1811 RC = &X86::GR32RegClass; in X86SelectShift()
1814 case Instruction::LShr: OpReg = X86::SHR32rCL; break; in X86SelectShift()
1815 case Instruction::AShr: OpReg = X86::SAR32rCL; break; in X86SelectShift()
1816 case Instruction::Shl: OpReg = X86::SHL32rCL; break; in X86SelectShift()
1819 CReg = X86::RCX; in X86SelectShift()
1820 RC = &X86::GR64RegClass; in X86SelectShift()
1823 case Instruction::LShr: OpReg = X86::SHR64rCL; break; in X86SelectShift()
1824 case Instruction::AShr: OpReg = X86::SAR64rCL; break; in X86SelectShift()
1825 case Instruction::Shl: OpReg = X86::SHL64rCL; break; in X86SelectShift()
1845 if (CReg != X86::CL) in X86SelectShift()
1847 TII.get(TargetOpcode::KILL), X86::CL) in X86SelectShift()
1888 { &X86::GR8RegClass, X86::AX, 0, { in X86SelectDivRem()
1889 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv in X86SelectDivRem()
1890 { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem in X86SelectDivRem()
1891 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv in X86SelectDivRem()
1892 { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem in X86SelectDivRem()
1895 { &X86::GR16RegClass, X86::AX, X86::DX, { in X86SelectDivRem()
1896 { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv in X86SelectDivRem()
1897 { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem in X86SelectDivRem()
1898 { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv in X86SelectDivRem()
1899 { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem in X86SelectDivRem()
1902 { &X86::GR32RegClass, X86::EAX, X86::EDX, { in X86SelectDivRem()
1903 { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv in X86SelectDivRem()
1904 { X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem in X86SelectDivRem()
1905 { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv in X86SelectDivRem()
1906 { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem in X86SelectDivRem()
1909 { &X86::GR64RegClass, X86::RAX, X86::RDX, { in X86SelectDivRem()
1910 { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv in X86SelectDivRem()
1911 { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem in X86SelectDivRem()
1912 { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv in X86SelectDivRem()
1913 { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem in X86SelectDivRem()
1960 Register Zero32 = createResultReg(&X86::GR32RegClass); in X86SelectDivRem()
1962 TII.get(X86::MOV32r0), Zero32); in X86SelectDivRem()
1970 .addReg(Zero32, 0, X86::sub_16bit); in X86SelectDivRem()
1978 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit); in X86SelectDivRem()
1996 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()
1997 Register SourceSuperReg = createResultReg(&X86::GR16RegClass); in X86SelectDivRem()
1998 Register ResultSuperReg = createResultReg(&X86::GR16RegClass); in X86SelectDivRem()
2000 TII.get(Copy), SourceSuperReg).addReg(X86::AX); in X86SelectDivRem()
2003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SHR16ri), in X86SelectDivRem()
2008 X86::sub_8bit); in X86SelectDivRem()
2035 X86::CondCode CC = X86::COND_NE; in X86FastEmitCMoveSelect()
2046 { X86::COND_NP, X86::COND_E, X86::TEST8rr }, in X86FastEmitCMoveSelect()
2047 { X86::COND_P, X86::COND_NE, X86::OR8rr } in X86FastEmitCMoveSelect()
2063 std::tie(CC, NeedSwap) = X86::getX86ConditionCode(Predicate); in X86FastEmitCMoveSelect()
2064 assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code."); in X86FastEmitCMoveSelect()
2077 Register FlagReg1 = createResultReg(&X86::GR8RegClass); in X86FastEmitCMoveSelect()
2078 Register FlagReg2 = createResultReg(&X86::GR8RegClass); in X86FastEmitCMoveSelect()
2079 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr), in X86FastEmitCMoveSelect()
2081 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr), in X86FastEmitCMoveSelect()
2085 Register TmpReg = createResultReg(&X86::GR8RegClass); in X86FastEmitCMoveSelect()
2115 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { in X86FastEmitCMoveSelect()
2117 CondReg = createResultReg(&X86::GR32RegClass); in X86FastEmitCMoveSelect()
2121 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); in X86FastEmitCMoveSelect()
2123 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::TEST8ri)) in X86FastEmitCMoveSelect()
2137 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(*RC)/8); in X86FastEmitCMoveSelect()
2198 const TargetRegisterClass *VR128X = &X86::VR128XRegClass; in X86FastEmitSSESelect()
2199 const TargetRegisterClass *VK1 = &X86::VK1RegClass; in X86FastEmitSSESelect()
2202 (RetVT == MVT::f32) ? X86::VCMPSSZrr : X86::VCMPSDZrr; in X86FastEmitSSESelect()
2215 (RetVT == MVT::f32) ? X86::VMOVSSZrrk : X86::VMOVSDZrrk; in X86FastEmitSSESelect()
2224 const TargetRegisterClass *VR128 = &X86::VR128RegClass; in X86FastEmitSSESelect()
2232 (RetVT == MVT::f32) ? X86::VCMPSSrr : X86::VCMPSDrr; in X86FastEmitSSESelect()
2234 (RetVT == MVT::f32) ? X86::VBLENDVPSrr : X86::VBLENDVPDrr; in X86FastEmitSSESelect()
2246 { X86::CMPSSrr, X86::ANDPSrr, X86::ANDNPSrr, X86::ORPSrr }, in X86FastEmitSSESelect()
2247 { X86::CMPSDrr, X86::ANDPDrr, X86::ANDNPDrr, X86::ORPDrr } in X86FastEmitSSESelect()
2257 const TargetRegisterClass *VR128 = &X86::VR128RegClass; in X86FastEmitSSESelect()
2276 case MVT::i8: Opc = X86::CMOV_GR8; break; in X86FastEmitPseudoSelect()
2277 case MVT::i16: Opc = X86::CMOV_GR16; break; in X86FastEmitPseudoSelect()
2278 case MVT::i32: Opc = X86::CMOV_GR32; break; in X86FastEmitPseudoSelect()
2280 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR16X : X86::CMOV_FR16; break; in X86FastEmitPseudoSelect()
2282 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR32X : X86::CMOV_FR32; break; in X86FastEmitPseudoSelect()
2284 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR64X : X86::CMOV_FR64; break; in X86FastEmitPseudoSelect()
2288 X86::CondCode CC = X86::COND_NE; in X86FastEmitPseudoSelect()
2296 std::tie(CC, NeedSwap) = X86::getX86ConditionCode(CI->getPredicate()); in X86FastEmitPseudoSelect()
2297 if (CC > X86::LAST_VALID_COND) in X86FastEmitPseudoSelect()
2315 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { in X86FastEmitPseudoSelect()
2317 CondReg = createResultReg(&X86::GR32RegClass); in X86FastEmitPseudoSelect()
2321 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); in X86FastEmitPseudoSelect()
2323 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::TEST8ri)) in X86FastEmitPseudoSelect()
2412 { { X86::VCVTSI2SSrr, X86::VCVTSI642SSrr }, in X86SelectIntToFP()
2413 { X86::VCVTSI2SDrr, X86::VCVTSI642SDrr } }, in X86SelectIntToFP()
2414 { { X86::VCVTSI2SSZrr, X86::VCVTSI642SSZrr }, in X86SelectIntToFP()
2415 { X86::VCVTSI2SDZrr, X86::VCVTSI642SDZrr } }, in X86SelectIntToFP()
2418 { X86::VCVTUSI2SSZrr, X86::VCVTUSI642SSZrr }, in X86SelectIntToFP()
2419 { X86::VCVTUSI2SDZrr, X86::VCVTUSI642SDZrr }, in X86SelectIntToFP()
2490 HasAVX512 ? X86::VCVTSS2SDZrr in X86SelectFPExt()
2491 : Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr; in X86SelectFPExt()
2504 HasAVX512 ? X86::VCVTSD2SSZrr in X86SelectFPTrunc()
2505 : Subtarget->hasAVX() ? X86::VCVTSD2SSrr : X86::CVTSD2SSrr; in X86SelectFPTrunc()
2535 X86::sub_8bit); in X86SelectTrunc()
2617 unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPS2PHZ128rr in fastLowerIntrinsicCall()
2618 : X86::VCVTPS2PHrr; in fastLowerIntrinsicCall()
2622 Opc = Subtarget->hasAVX512() ? X86::VMOVPDI2DIZrr in fastLowerIntrinsicCall()
2623 : X86::VMOVPDI2DIrr; in fastLowerIntrinsicCall()
2624 ResultReg = createResultReg(&X86::GR32RegClass); in fastLowerIntrinsicCall()
2629 unsigned RegIdx = X86::sub_16bit; in fastLowerIntrinsicCall()
2640 unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPH2PSZ128rr in fastLowerIntrinsicCall()
2641 : X86::VCVTPH2PSrr; in fastLowerIntrinsicCall()
2671 case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break; in fastLowerIntrinsicCall()
2672 case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break; in fastLowerIntrinsicCall()
2682 assert(((FrameReg == X86::RBP && VT == MVT::i64) || in fastLowerIntrinsicCall()
2683 (FrameReg == X86::EBP && VT == MVT::i32)) && in fastLowerIntrinsicCall()
2784 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::TRAP)); in fastLowerIntrinsicCall()
2801 { X86::SQRTSSr, X86::SQRTSDr }, in fastLowerIntrinsicCall()
2802 { X86::VSQRTSSr, X86::VSQRTSDr }, in fastLowerIntrinsicCall()
2803 { X86::VSQRTSSZr, X86::VSQRTSDZr }, in fastLowerIntrinsicCall()
2875 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2877 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2879 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2881 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2883 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2885 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2896 { X86::INC8r, X86::INC16r, X86::INC32r, X86::INC64r }, in fastLowerIntrinsicCall()
2897 { X86::DEC8r, X86::DEC16r, X86::DEC32r, X86::DEC64r } in fastLowerIntrinsicCall()
2901 CondCode == X86::COND_O) { in fastLowerIntrinsicCall()
2924 { X86::MUL8r, X86::MUL16r, X86::MUL32r, X86::MUL64r }; in fastLowerIntrinsicCall()
2925 static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX }; in fastLowerIntrinsicCall()
2935 { X86::IMUL8r, X86::IMUL16rr, X86::IMUL32rr, X86::IMUL64rr }; in fastLowerIntrinsicCall()
2940 TII.get(TargetOpcode::COPY), X86::AL) in fastLowerIntrinsicCall()
2952 Register ResultReg2 = createResultReg(&X86::GR8RegClass); in fastLowerIntrinsicCall()
2954 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::SETCCr), in fastLowerIntrinsicCall()
2987 { { X86::CVTTSS2SIrr, X86::CVTTSS2SI64rr }, in fastLowerIntrinsicCall()
2988 { X86::CVTTSD2SIrr, X86::CVTTSD2SI64rr } }, in fastLowerIntrinsicCall()
2989 { { X86::VCVTTSS2SIrr, X86::VCVTTSS2SI64rr }, in fastLowerIntrinsicCall()
2990 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SI64rr } }, in fastLowerIntrinsicCall()
2991 { { X86::VCVTTSS2SIZrr, X86::VCVTTSS2SI64Zrr }, in fastLowerIntrinsicCall()
2992 { X86::VCVTTSD2SIZrr, X86::VCVTTSD2SI64Zrr } }, in fastLowerIntrinsicCall()
3051 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r8); in fastLowerIntrinsicCall()
3052 RC = &X86::GR32RegClass; in fastLowerIntrinsicCall()
3055 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r16); in fastLowerIntrinsicCall()
3056 RC = &X86::GR32RegClass; in fastLowerIntrinsicCall()
3059 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r32); in fastLowerIntrinsicCall()
3060 RC = &X86::GR32RegClass; in fastLowerIntrinsicCall()
3063 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r64r64); in fastLowerIntrinsicCall()
3064 RC = &X86::GR64RegClass; in fastLowerIntrinsicCall()
3149 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D in fastLowerArguments()
3152 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9 in fastLowerArguments()
3155 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in fastLowerArguments()
3156 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 in fastLowerArguments()
3477 TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base); in fastLowerCall()
3491 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, in fastLowerCall()
3492 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 in fastLowerCall()
3497 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::MOV8ri), in fastLowerCall()
3498 X86::AL).addImm(NumXMMRegs); in fastLowerCall()
3520 unsigned CallOpc = Is64Bit ? X86::CALL64r : X86::CALL32r; in fastLowerCall()
3540 ? (Is64Bit ? X86::CALL64m : X86::CALL32m) in fastLowerCall()
3541 : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32); in fastLowerCall()
3545 MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0); in fastLowerCall()
3560 MIB.addReg(X86::EBX, RegState::Implicit); in fastLowerCall()
3563 MIB.addReg(X86::AL, RegState::Implicit); in fastLowerCall()
3571 X86::isCalleePop(CC, Subtarget->is64Bit(), IsVarArg, in fastLowerCall()
3601 if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) && in fastLowerCall()
3604 CopyReg = createResultReg(&X86::RFP80RegClass); in fastLowerCall()
3617 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall()
3623 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
3730 Register SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass); in X86MaterializeInt()
3735 return fastEmitInst_extractsubreg(MVT::i8, SrcReg, X86::sub_8bit); in X86MaterializeInt()
3737 return fastEmitInst_extractsubreg(MVT::i16, SrcReg, X86::sub_16bit); in X86MaterializeInt()
3741 Register ResultReg = createResultReg(&X86::GR64RegClass); in X86MaterializeInt()
3744 .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit); in X86MaterializeInt()
3756 case MVT::i8: Opc = X86::MOV8ri; break; in X86MaterializeInt()
3757 case MVT::i16: Opc = X86::MOV16ri; break; in X86MaterializeInt()
3758 case MVT::i32: Opc = X86::MOV32ri; break; in X86MaterializeInt()
3761 Opc = X86::MOV32ri64; in X86MaterializeInt()
3763 Opc = X86::MOV64ri32; in X86MaterializeInt()
3765 Opc = X86::MOV64ri; in X86MaterializeInt()
3791 Opc = HasAVX512 ? X86::VMOVSSZrm_alt in X86MaterializeFP()
3792 : HasAVX ? X86::VMOVSSrm_alt in X86MaterializeFP()
3793 : HasSSE1 ? X86::MOVSSrm_alt in X86MaterializeFP()
3794 : X86::LD_Fp32m; in X86MaterializeFP()
3797 Opc = HasAVX512 ? X86::VMOVSDZrm_alt in X86MaterializeFP()
3798 : HasAVX ? X86::VMOVSDrm_alt in X86MaterializeFP()
3799 : HasSSE2 ? X86::MOVSDrm_alt in X86MaterializeFP()
3800 : X86::LD_Fp64m; in X86MaterializeFP()
3818 PICBase = X86::RIP; in X86MaterializeFP()
3826 Register AddrReg = createResultReg(&X86::GR64RegClass); in X86MaterializeFP()
3827 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::MOV64ri), in X86MaterializeFP()
3868 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(X86::MOV64ri), in X86MaterializeGV()
3874 ? (Subtarget->isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r) in X86MaterializeGV()
3875 : X86::LEA64r; in X86MaterializeGV()
3905 Opc = X86::LD_Fp032; in fastMaterializeConstant()
3909 Opc = X86::LD_Fp064; in fastMaterializeConstant()
3912 Opc = X86::LD_Fp080; in fastMaterializeConstant()
3944 ? (Subtarget->isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r) in fastMaterializeAlloca()
3945 : X86::LEA64r; in fastMaterializeAlloca()
3966 Opc = HasAVX512 ? X86::AVX512_FsFLD0SH : X86::FsFLD0SH; in fastMaterializeFloatZero()
3969 Opc = HasAVX512 ? X86::AVX512_FsFLD0SS in fastMaterializeFloatZero()
3970 : HasSSE1 ? X86::FsFLD0SS in fastMaterializeFloatZero()
3971 : X86::LD_Fp032; in fastMaterializeFloatZero()
3974 Opc = HasAVX512 ? X86::AVX512_FsFLD0SD in fastMaterializeFloatZero()
3975 : HasSSE2 ? X86::FsFLD0SD in fastMaterializeFloatZero()
3976 : X86::LD_Fp064; in fastMaterializeFloatZero()
4068 FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo, in createFastISel()