Lines Matching refs:Opc
86 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
120 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
333 unsigned Opc = 0; in X86FastEmitLoad() local
337 Opc = X86::MOV8rm; in X86FastEmitLoad()
340 Opc = X86::MOV16rm; in X86FastEmitLoad()
343 Opc = X86::MOV32rm; in X86FastEmitLoad()
347 Opc = X86::MOV64rm; in X86FastEmitLoad()
350 Opc = HasAVX512 ? X86::VMOVSSZrm_alt in X86FastEmitLoad()
356 Opc = HasAVX512 ? X86::VMOVSDZrm_alt in X86FastEmitLoad()
366 Opc = HasVLX ? X86::VMOVNTDQAZ128rm : in X86FastEmitLoad()
369 Opc = HasVLX ? X86::VMOVAPSZ128rm : in X86FastEmitLoad()
372 Opc = HasVLX ? X86::VMOVUPSZ128rm : in X86FastEmitLoad()
377 Opc = HasVLX ? X86::VMOVNTDQAZ128rm : in X86FastEmitLoad()
380 Opc = HasVLX ? X86::VMOVAPDZ128rm : in X86FastEmitLoad()
383 Opc = HasVLX ? X86::VMOVUPDZ128rm : in X86FastEmitLoad()
391 Opc = HasVLX ? X86::VMOVNTDQAZ128rm : in X86FastEmitLoad()
394 Opc = HasVLX ? X86::VMOVDQA64Z128rm : in X86FastEmitLoad()
397 Opc = HasVLX ? X86::VMOVDQU64Z128rm : in X86FastEmitLoad()
403 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; in X86FastEmitLoad()
407 Opc = HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm; in X86FastEmitLoad()
409 Opc = HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm; in X86FastEmitLoad()
414 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; in X86FastEmitLoad()
418 Opc = HasVLX ? X86::VMOVAPDZ256rm : X86::VMOVAPDYrm; in X86FastEmitLoad()
420 Opc = HasVLX ? X86::VMOVUPDZ256rm : X86::VMOVUPDYrm; in X86FastEmitLoad()
428 Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; in X86FastEmitLoad()
432 Opc = HasVLX ? X86::VMOVDQA64Z256rm : X86::VMOVDQAYrm; in X86FastEmitLoad()
434 Opc = HasVLX ? X86::VMOVDQU64Z256rm : X86::VMOVDQUYrm; in X86FastEmitLoad()
439 Opc = X86::VMOVNTDQAZrm; in X86FastEmitLoad()
441 Opc = (Alignment >= 64) ? X86::VMOVAPSZrm : X86::VMOVUPSZrm; in X86FastEmitLoad()
446 Opc = X86::VMOVNTDQAZrm; in X86FastEmitLoad()
448 Opc = (Alignment >= 64) ? X86::VMOVAPDZrm : X86::VMOVUPDZrm; in X86FastEmitLoad()
458 Opc = X86::VMOVNTDQAZrm; in X86FastEmitLoad()
460 Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm; in X86FastEmitLoad()
468 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg); in X86FastEmitLoad()
490 unsigned Opc = 0; in X86FastEmitStore() local
503 case MVT::i8: Opc = X86::MOV8mr; break; in X86FastEmitStore()
504 case MVT::i16: Opc = X86::MOV16mr; break; in X86FastEmitStore()
506 Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTImr : X86::MOV32mr; in X86FastEmitStore()
510 Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTI_64mr : X86::MOV64mr; in X86FastEmitStore()
515 Opc = X86::MOVNTSS; in X86FastEmitStore()
517 Opc = HasAVX512 ? X86::VMOVSSZmr : in X86FastEmitStore()
520 Opc = X86::ST_Fp32m; in X86FastEmitStore()
525 Opc = X86::MOVNTSD; in X86FastEmitStore()
527 Opc = HasAVX512 ? X86::VMOVSDZmr : in X86FastEmitStore()
530 Opc = X86::ST_Fp64m; in X86FastEmitStore()
533 Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr; in X86FastEmitStore()
538 Opc = HasVLX ? X86::VMOVNTPSZ128mr : in X86FastEmitStore()
541 Opc = HasVLX ? X86::VMOVAPSZ128mr : in X86FastEmitStore()
544 Opc = HasVLX ? X86::VMOVUPSZ128mr : in X86FastEmitStore()
550 Opc = HasVLX ? X86::VMOVNTPDZ128mr : in X86FastEmitStore()
553 Opc = HasVLX ? X86::VMOVAPDZ128mr : in X86FastEmitStore()
556 Opc = HasVLX ? X86::VMOVUPDZ128mr : in X86FastEmitStore()
565 Opc = HasVLX ? X86::VMOVNTDQZ128mr : in X86FastEmitStore()
568 Opc = HasVLX ? X86::VMOVDQA64Z128mr : in X86FastEmitStore()
571 Opc = HasVLX ? X86::VMOVDQU64Z128mr : in X86FastEmitStore()
578 Opc = HasVLX ? X86::VMOVNTPSZ256mr : X86::VMOVNTPSYmr; in X86FastEmitStore()
580 Opc = HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr; in X86FastEmitStore()
582 Opc = HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr; in X86FastEmitStore()
588 Opc = HasVLX ? X86::VMOVNTPDZ256mr : X86::VMOVNTPDYmr; in X86FastEmitStore()
590 Opc = HasVLX ? X86::VMOVAPDZ256mr : X86::VMOVAPDYmr; in X86FastEmitStore()
592 Opc = HasVLX ? X86::VMOVUPDZ256mr : X86::VMOVUPDYmr; in X86FastEmitStore()
601 Opc = HasVLX ? X86::VMOVNTDQZ256mr : X86::VMOVNTDQYmr; in X86FastEmitStore()
603 Opc = HasVLX ? X86::VMOVDQA64Z256mr : X86::VMOVDQAYmr; in X86FastEmitStore()
605 Opc = HasVLX ? X86::VMOVDQU64Z256mr : X86::VMOVDQUYmr; in X86FastEmitStore()
610 Opc = IsNonTemporal ? X86::VMOVNTPSZmr : X86::VMOVAPSZmr; in X86FastEmitStore()
612 Opc = X86::VMOVUPSZmr; in X86FastEmitStore()
617 Opc = IsNonTemporal ? X86::VMOVNTPDZmr : X86::VMOVAPDZmr; in X86FastEmitStore()
619 Opc = X86::VMOVUPDZmr; in X86FastEmitStore()
629 Opc = IsNonTemporal ? X86::VMOVNTDQZmr : X86::VMOVDQA64Zmr; in X86FastEmitStore()
631 Opc = X86::VMOVDQU64Zmr; in X86FastEmitStore()
635 const MCInstrDesc &Desc = TII.get(Opc); in X86FastEmitStore()
661 unsigned Opc = 0; in X86FastEmitStore() local
668 case MVT::i8: Opc = X86::MOV8mi; break; in X86FastEmitStore()
669 case MVT::i16: Opc = X86::MOV16mi; break; in X86FastEmitStore()
670 case MVT::i32: Opc = X86::MOV32mi; break; in X86FastEmitStore()
674 Opc = X86::MOV64mi32; in X86FastEmitStore()
678 if (Opc) { in X86FastEmitStore()
680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc)); in X86FastEmitStore()
699 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument
702 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
768 unsigned Opc = 0; in handleConstantAddresses() local
779 Opc = X86::MOV64rm; in handleConstantAddresses()
782 Opc = X86::MOV32rm; in handleConstantAddresses()
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), LoadReg); in handleConstantAddresses()
2137 unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(*RC)/8); in X86FastEmitCMoveSelect() local
2138 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); in X86FastEmitCMoveSelect()
2250 const uint16_t *Opc = nullptr; in X86FastEmitSSESelect() local
2253 case MVT::f32: Opc = &OpcTable[0][0]; break; in X86FastEmitSSESelect()
2254 case MVT::f64: Opc = &OpcTable[1][0]; break; in X86FastEmitSSESelect()
2258 Register CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpRHSReg, CC); in X86FastEmitSSESelect()
2259 Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg); in X86FastEmitSSESelect()
2260 Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, RHSReg); in X86FastEmitSSESelect()
2261 Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, AndReg); in X86FastEmitSSESelect()
2273 unsigned Opc; in X86FastEmitPseudoSelect() local
2276 case MVT::i8: Opc = X86::CMOV_GR8; break; in X86FastEmitPseudoSelect()
2277 case MVT::i16: Opc = X86::CMOV_GR16; break; in X86FastEmitPseudoSelect()
2278 case MVT::i32: Opc = X86::CMOV_GR32; break; in X86FastEmitPseudoSelect()
2280 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR16X : X86::CMOV_FR16; break; in X86FastEmitPseudoSelect()
2282 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR32X : X86::CMOV_FR32; break; in X86FastEmitPseudoSelect()
2284 Opc = Subtarget->hasAVX512() ? X86::CMOV_FR64X : X86::CMOV_FR64; break; in X86FastEmitPseudoSelect()
2339 fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); in X86FastEmitPseudoSelect()
2489 unsigned Opc = in X86SelectFPExt() local
2492 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64)); in X86SelectFPExt()
2503 unsigned Opc = in X86SelectFPTrunc() local
2506 return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32)); in X86SelectFPTrunc()
2617 unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPS2PHZ128rr in fastLowerIntrinsicCall() local
2619 InputReg = fastEmitInst_ri(Opc, RC, InputReg, 4); in fastLowerIntrinsicCall()
2622 Opc = Subtarget->hasAVX512() ? X86::VMOVPDI2DIZrr in fastLowerIntrinsicCall()
2625 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
2640 unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPH2PSZ128rr in fastLowerIntrinsicCall() local
2642 InputReg = fastEmitInst_r(Opc, RC, InputReg); in fastLowerIntrinsicCall()
2666 unsigned Opc; in fastLowerIntrinsicCall() local
2671 case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break; in fastLowerIntrinsicCall()
2672 case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break; in fastLowerIntrinsicCall()
2702 TII.get(Opc), DestReg), SrcReg); in fastLowerIntrinsicCall()
2808 unsigned Opc; in fastLowerIntrinsicCall() local
2811 case MVT::f32: Opc = SqrtOpc[AVXLevel][0]; break; in fastLowerIntrinsicCall()
2812 case MVT::f64: Opc = SqrtOpc[AVXLevel][1]; break; in fastLowerIntrinsicCall()
2831 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), in fastLowerIntrinsicCall()
2895 static const uint16_t Opc[2][4] = { in fastLowerIntrinsicCall() local
2906 TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg) in fastLowerIntrinsicCall()
2997 unsigned Opc; in fastLowerIntrinsicCall() local
3000 case MVT::i32: Opc = CvtOpc[AVXLevel][IsInputDouble][0]; break; in fastLowerIntrinsicCall()
3001 case MVT::i64: Opc = CvtOpc[AVXLevel][IsInputDouble][1]; break; in fastLowerIntrinsicCall()
3024 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
3043 unsigned Opc; in fastLowerIntrinsicCall() local
3051 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r8); in fastLowerIntrinsicCall()
3055 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r16); in fastLowerIntrinsicCall()
3059 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r32r32); in fastLowerIntrinsicCall()
3063 Opc = GET_EGPR_IF_ENABLED(X86::CRC32r64r64); in fastLowerIntrinsicCall()
3077 Register ResultReg = fastEmitInst_rr(Opc, RC, LHSReg, RHSReg); in fastLowerIntrinsicCall()
3617 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in fastLowerCall() local
3621 TII.get(Opc)), FI) in fastLowerCall()
3623 Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; in fastLowerCall()
3625 TII.get(Opc), ResultReg + i), FI); in fastLowerCall()
3750 unsigned Opc = 0; in X86MaterializeInt() local
3756 case MVT::i8: Opc = X86::MOV8ri; break; in X86MaterializeInt()
3757 case MVT::i16: Opc = X86::MOV16ri; break; in X86MaterializeInt()
3758 case MVT::i32: Opc = X86::MOV32ri; break; in X86MaterializeInt()
3761 Opc = X86::MOV32ri64; in X86MaterializeInt()
3763 Opc = X86::MOV64ri32; in X86MaterializeInt()
3765 Opc = X86::MOV64ri; in X86MaterializeInt()
3769 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in X86MaterializeInt()
3783 unsigned Opc = 0; in X86MaterializeFP() local
3791 Opc = HasAVX512 ? X86::VMOVSSZrm_alt in X86MaterializeFP()
3797 Opc = HasAVX512 ? X86::VMOVSDZrm_alt in X86MaterializeFP()
3831 TII.get(Opc), ResultReg); in X86MaterializeFP()
3841 TII.get(Opc), ResultReg), in X86MaterializeFP()
3872 unsigned Opc = in X86MaterializeGV() local
3877 TII.get(Opc), ResultReg), AM); in X86MaterializeGV()
3899 unsigned Opc = 0; in fastMaterializeConstant() local
3905 Opc = X86::LD_Fp032; in fastMaterializeConstant()
3909 Opc = X86::LD_Fp064; in fastMaterializeConstant()
3912 Opc = X86::LD_Fp080; in fastMaterializeConstant()
3916 if (Opc) { in fastMaterializeConstant()
3918 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), in fastMaterializeConstant()
3942 unsigned Opc = in fastMaterializeAlloca() local
3949 TII.get(Opc), ResultReg), AM); in fastMaterializeAlloca()
3962 unsigned Opc = 0; in fastMaterializeFloatZero() local
3966 Opc = HasAVX512 ? X86::AVX512_FsFLD0SH : X86::FsFLD0SH; in fastMaterializeFloatZero()
3969 Opc = HasAVX512 ? X86::AVX512_FsFLD0SS in fastMaterializeFloatZero()
3974 Opc = HasAVX512 ? X86::AVX512_FsFLD0SD in fastMaterializeFloatZero()
3984 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg); in fastMaterializeFloatZero()