Lines Matching refs:vec
167 foreach vec = AllVecs in {
168 defm : LoadPat<vec.vt, load, "LOAD_V128">;
196 foreach vec = AllVecs in {
197 defvar inst = "LOAD"#vec.lane_bits#"_SPLAT";
198 defm : LoadPat<vec.vt,
199 PatFrag<(ops node:$addr), (splat_vector (vec.lane_vt (vec.lane_load node:$addr)))>,
204 multiclass SIMDLoadExtend<Vec vec, string loadPat, bits<32> simdop> {
205 defvar signed = vec.prefix#".load"#loadPat#"_s";
206 defvar unsigned = vec.prefix#".load"#loadPat#"_u";
208 defm LOAD_EXTEND_S_#vec#_A32 :
214 defm LOAD_EXTEND_U_#vec#_A32 :
220 defm LOAD_EXTEND_S_#vec#_A64 :
226 defm LOAD_EXTEND_U_#vec#_A64 :
239 foreach vec = [I16x8, I32x4, I64x2] in
243 defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits);
244 defvar inst = "LOAD_EXTEND"#exts[1]#"_"#vec;
245 defm : LoadPat<vec.vt, loadpat, inst>;
249 multiclass SIMDLoadZero<Vec vec, bits<32> simdop> {
250 defvar name = "v128.load"#vec.lane_bits#"_zero";
252 defm LOAD_ZERO_#vec#_A32 :
258 defm LOAD_ZERO_#vec#_A64 :
272 foreach vec = [I32x4, I64x2] in {
273 defvar inst = "LOAD_ZERO_"#vec;
274 defvar pat = PatFrag<(ops node:$addr), (scalar_to_vector (vec.lane_vt (load $addr)))>;
275 defm : LoadPat<vec.vt, pat, inst>;
279 foreach vec = [I32x4, I64x2] in {
280 defvar inst = "LOAD_ZERO_"#vec;
282 (vector_insert (vec.splat (vec.lane_vt 0)), (vec.lane_vt (load $ptr)), 0)>;
283 defm : LoadPat<vec.vt, pat, inst>;
287 multiclass SIMDLoadLane<Vec vec, bits<32> simdop> {
288 defvar name = "v128.load"#vec.lane_bits#"_lane";
290 defm LOAD_LANE_#vec#_A32 :
293 I32:$addr, V128:$vec),
295 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
297 defm LOAD_LANE_#vec#_A64 :
300 I64:$addr, V128:$vec),
302 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
313 multiclass LoadLanePatNoOffset<Vec vec, SDPatternOperator kind> {
314 defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32");
315 defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64");
316 def : Pat<(vec.vt (kind (i32 I32:$addr),
317 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
318 (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
320 def : Pat<(vec.vt (kind (i64 I64:$addr),
321 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
322 (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>,
327 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
328 (vector_insert $vec, (i32 (extloadi8 $ptr)), $idx)>;
330 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
331 (vector_insert $vec, (i32 (extloadi16 $ptr)), $idx)>;
333 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
334 (vector_insert $vec, (i32 (load $ptr)), $idx)>;
336 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
337 (vector_insert $vec, (i64 (load $ptr)), $idx)>;
351 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
353 "v128.store\t${off}(${addr})$p2align, $vec",
356 SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, V128:$vec),
358 "v128.store\t${off}(${addr})$p2align, $vec",
363 foreach vec = AllVecs in {
364 defm : StorePat<vec.vt, store, "STORE_V128">;
368 multiclass SIMDStoreLane<Vec vec, bits<32> simdop> {
369 defvar name = "v128.store"#vec.lane_bits#"_lane";
371 defm STORE_LANE_#vec#_A32 :
374 I32:$addr, V128:$vec),
376 [], name#"\t${off}(${addr})$p2align, $vec, $idx",
378 defm STORE_LANE_#vec#_A64 :
381 I64:$addr, V128:$vec),
383 [], name#"\t${off}(${addr})$p2align, $vec, $idx",
393 multiclass StoreLanePat<Vec vec, SDPatternOperator kind> {
395 (vec.vt V128:$vec),
396 (i32 vec.lane_idx:$idx)),
397 (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, $offset, imm:$idx, $addr, $vec)>,
400 (vec.vt V128:$vec),
401 (i32 vec.lane_idx:$idx)),
402 (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, $offset, imm:$idx, $addr, $vec)>,
407 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
408 (truncstorei8 (i32 (vector_extract $vec, $idx)), $ptr)>;
410 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
411 (truncstorei16 (i32 (vector_extract $vec, $idx)), $ptr)>;
413 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
414 (store (i32 (vector_extract $vec, $idx)), $ptr)>;
416 PatFrag<(ops node:$ptr, node:$vec, node:$idx),
417 (store (i64 (vector_extract $vec, $idx)), $ptr)>;
432 multiclass ConstVec<Vec vec, dag ops, dag pat, string args> {
434 defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops,
435 [(set V128:$dst, (vec.vt pat))],
487 foreach vec = AllVecs in {
488 defvar numEls = !div(vec.vt.Size, vec.lane_bits);
489 defvar isFloat = !or(!eq(vec.lane_vt, f32), !eq(vec.lane_vt, f64));
491 def : Pat<(vec.splat (vec.lane_vt immKind:$x)),
492 !dag(!cast<NI>("CONST_V128_"#vec),
493 !listsplat((vec.lane_vt immKind:$x), numEls),
531 foreach vec = AllVecs in {
533 def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
548 def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
576 multiclass Splat<Vec vec, bits<32> simdop> {
577 defm SPLAT_#vec : SIMD_I<(outs V128:$dst), (ins vec.lane_rc:$x),
579 [(set (vec.vt V128:$dst),
580 (vec.splat vec.lane_rc:$x))],
581 vec.prefix#".splat\t$dst, $x", vec.prefix#".splat",
593 foreach vec = AllVecs in
594 def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))),
595 (!cast<Instruction>("SPLAT_"#vec) $x)>;
602 multiclass ExtractLane<Vec vec, bits<32> simdop, string suffix = ""> {
603 defm EXTRACT_LANE_#vec#suffix :
604 SIMD_I<(outs vec.lane_rc:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
606 vec.prefix#".extract_lane"#suffix#"\t$dst, $vec, $idx",
607 vec.prefix#".extract_lane"#suffix#"\t$idx", simdop>;
619 def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)),
620 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
621 def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)),
622 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
623 def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)),
624 (EXTRACT_LANE_I32x4 $vec, imm:$idx)>;
625 def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)),
626 (EXTRACT_LANE_F32x4 $vec, imm:$idx)>;
627 def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)),
628 (EXTRACT_LANE_I64x2 $vec, imm:$idx)>;
629 def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)),
630 (EXTRACT_LANE_F64x2 $vec, imm:$idx)>;
633 (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8),
634 (EXTRACT_LANE_I8x16_s $vec, imm:$idx)>;
636 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)),
637 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
639 (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16),
640 (EXTRACT_LANE_I16x8_s $vec, imm:$idx)>;
642 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)),
643 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
646 multiclass ReplaceLane<Vec vec, bits<32> simdop> {
647 defm REPLACE_LANE_#vec :
648 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, vec.lane_rc:$x),
651 (vec.vt V128:$vec),
652 (vec.lane_vt vec.lane_rc:$x),
653 (i32 vec.lane_idx:$idx)))],
654 vec.prefix#".replace_lane\t$dst, $vec, $idx, $x",
655 vec.prefix#".replace_lane\t$idx", simdop>;
666 def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
667 (REPLACE_LANE_I8x16 $vec, 0, $x)>;
668 def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
669 (REPLACE_LANE_I16x8 $vec, 0, $x)>;
670 def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
671 (REPLACE_LANE_I32x4 $vec, 0, $x)>;
672 def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
673 (REPLACE_LANE_I64x2 $vec, 0, $x)>;
674 def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
675 (REPLACE_LANE_F32x4 $vec, 0, $x)>;
676 def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
677 (REPLACE_LANE_F64x2 $vec, 0, $x)>;
683 multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> {
684 defm _#vec :
686 [(set (vec.int_vt V128:$dst),
687 (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))],
688 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
689 vec.prefix#"."#name, simdop>;
758 multiclass SIMDBinary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> {
759 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
761 [(set (vec.vt V128:$dst),
762 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
763 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
764 vec.prefix#"."#name, simdop>;
773 foreach vec = IntVecs in
774 def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
778 multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> {
779 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins),
780 [(set (vec.vt V128:$dst),
781 (vec.vt (node (vec.vt V128:$v))))],
782 vec.prefix#"."#name#"\t$dst, $v",
783 vec.prefix#"."#name, simdop>;
789 foreach vec = IntVecs in
790 def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>;
806 foreach vec = AllVecs in
807 def : Pat<(vec.vt (int_wasm_bitselect
808 (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))),
812 foreach vec = IntVecs in
813 def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)),
814 (and (vnot V128:$c), (vec.vt V128:$v2)))),
818 foreach vec = IntVecs in
819 def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)),
820 (vec.vt V128:$c)),
821 (vec.vt V128:$v2))),
825 foreach vec = IntVecs in
826 def : Pat<(vec.vt (xor (and (xor (vec.vt V128:$v1), (vec.vt V128:$v2)),
827 (vnot (vec.vt V128:$c))),
828 (vec.vt V128:$v2))),
832 foreach vec = AllVecs in
833 def : Pat<(vec.vt (vselect
834 (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))),
842 foreach vec = AllVecs in {
843 def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
850 (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
855 (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
857 } // foreach vec
883 defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [],
884 "v128.any_true\t$dst, $vec", "v128.any_true", 0x53>;
886 foreach vec = IntVecs in
887 def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>;
890 multiclass SIMDAllTrue<Vec vec, bits<32> simdop> {
891 defm ALLTRUE_#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
893 (i32 (int_wasm_alltrue (vec.vt V128:$vec))))],
894 vec.prefix#".all_true\t$dst, $vec",
895 vec.prefix#".all_true", simdop>;
916 defvar vec = !cast<Vec>(reduction[2]);
917 def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
918 def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
919 def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
922 multiclass SIMDBitmask<Vec vec, bits<32> simdop> {
923 defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
925 (i32 (int_wasm_bitmask (vec.vt V128:$vec))))],
926 vec.prefix#".bitmask\t$dst, $vec", vec.prefix#".bitmask",
939 multiclass SIMDShift<Vec vec, SDNode node, string name, bits<32> simdop> {
940 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), (outs), (ins),
941 [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))],
942 vec.prefix#"."#name#"\t$dst, $vec, $x",
943 vec.prefix#"."#name, simdop>;
1063 foreach vec = [I8x16, I16x8] in {
1064 defvar inst = !cast<NI>("AVGR_U_"#vec);
1067 (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
1068 (vec.splat (i32 1))),
1087 multiclass SIMDExtBinary<Vec vec, SDPatternOperator node, string name,
1089 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
1091 [(set (vec.vt V128:$dst), (node
1092 (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))],
1093 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
1094 vec.prefix#"."#name, simdop>;
1219 foreach vec = [F32x4, F64x2] in {
1220 defvar pmin = !cast<NI>("PMIN_"#vec);
1221 defvar pmax = !cast<NI>("PMAX_"#vec);
1222 def : Pat<(vec.int_vt (vselect
1223 (setolt (vec.vt (bitconvert V128:$rhs)),
1224 (vec.vt (bitconvert V128:$lhs))),
1227 def : Pat<(vec.int_vt (vselect
1228 (setolt (vec.vt (bitconvert V128:$lhs)),
1229 (vec.vt (bitconvert V128:$rhs))),
1248 multiclass SIMDConvert<Vec vec, Vec arg, SDPatternOperator op, string name,
1250 defm op#_#vec :
1251 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
1252 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1253 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
1287 multiclass SIMDExtend<Vec vec, bits<32> baseInst> {
1288 defm "" : SIMDConvert<vec, vec.split, extend_low_s,
1289 "extend_low_"#vec.split.prefix#"_s", baseInst>;
1290 defm "" : SIMDConvert<vec, vec.split, extend_high_s,
1291 "extend_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>;
1292 defm "" : SIMDConvert<vec, vec.split, extend_low_u,
1293 "extend_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>;
1294 defm "" : SIMDConvert<vec, vec.split, extend_high_u,
1295 "extend_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>;
1303 multiclass SIMDNarrow<Vec vec, bits<32> baseInst> {
1304 defvar name = vec.split.prefix#".narrow_"#vec.prefix;
1305 defm NARROW_S_#vec.split :
1307 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed
1308 (vec.vt V128:$low), (vec.vt V128:$high))))],
1310 defm NARROW_U_#vec.split :
1312 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned
1313 (vec.vt V128:$low), (vec.vt V128:$high))))],
1389 multiclass RelaxedConvert<Vec vec, Vec arg, SDPatternOperator op, string name, bits<32> simdop> {
1390 defm op#_#vec :
1391 RELAXED_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
1392 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1393 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
1409 multiclass SIMDMADD<Vec vec, bits<32> simdopA, bits<32> simdopS> {
1410 defm MADD_#vec :
1412 [(set (vec.vt V128:$dst), (int_wasm_relaxed_madd
1413 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1414 vec.prefix#".relaxed_madd\t$dst, $a, $b, $c",
1415 vec.prefix#".relaxed_madd", simdopA>;
1416 defm NMADD_#vec :
1418 [(set (vec.vt V128:$dst), (int_wasm_relaxed_nmadd
1419 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1420 vec.prefix#".relaxed_nmadd\t$dst, $a, $b, $c",
1421 vec.prefix#".relaxed_nmadd", simdopS>;
1431 multiclass SIMDLANESELECT<Vec vec, bits<32> op> {
1432 defm LANESELECT_#vec :
1434 [(set (vec.vt V128:$dst), (int_wasm_relaxed_laneselect
1435 (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1436 vec.prefix#".relaxed_laneselect\t$dst, $a, $b, $c",
1437 vec.prefix#".relaxed_laneselect", op>;
1449 multiclass RelaxedBinary<Vec vec, SDPatternOperator node, string name,
1451 defm _#vec : RELAXED_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
1453 [(set (vec.vt V128:$dst),
1454 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
1455 vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
1456 vec.prefix#"."#name, simdop>;