Lines Matching refs:VecT
1900 MVT VecT = Extract.getOperand(0).getSimpleValueType(); in LowerSIGN_EXTEND_INREG() local
1901 if (VecT.getVectorElementType().getSizeInBits() > 32) in LowerSIGN_EXTEND_INREG()
1907 if (ExtractedVecT == VecT) in LowerSIGN_EXTEND_INREG()
1916 ExtractedVecT.getVectorNumElements() / VecT.getVectorNumElements(); in LowerSIGN_EXTEND_INREG()
2040 const EVT VecT = Op.getValueType(); in LowerBUILD_VECTOR() local
2043 bool CanSwizzle = VecT == MVT::v16i8; in LowerBUILD_VECTOR()
2094 VecT.getVectorNumElements()) in LowerBUILD_VECTOR()
2180 Result = DAG.getNode(WebAssemblyISD::SWIZZLE, DL, VecT, SwizzleSrc, in LowerBUILD_VECTOR()
2188 size_t DestLaneSize = VecT.getVectorElementType().getFixedSizeInBits() / 8; in LowerBUILD_VECTOR()
2189 size_t DestLaneCount = VecT.getVectorNumElements(); in LowerBUILD_VECTOR()
2193 SDValue Src2 = ShuffleSrc2 ? ShuffleSrc2 : DAG.getUNDEF(VecT); in LowerBUILD_VECTOR()
2194 if (Src1.getValueType() != VecT) { in LowerBUILD_VECTOR()
2199 Src1 = DAG.getBitcast(VecT, Src1); in LowerBUILD_VECTOR()
2201 if (Src2.getValueType() != VecT) { in LowerBUILD_VECTOR()
2206 Src2 = DAG.getBitcast(VecT, Src2); in LowerBUILD_VECTOR()
2223 Result = DAG.getVectorShuffle(VecT, DL, Src1, Src2, MaskRef); in LowerBUILD_VECTOR()
2256 Result = DAG.getBuildVector(VecT, DL, ConstLanes); in LowerBUILD_VECTOR()
2262 Result = DAG.getSplatBuildVector(VecT, DL, SplatValue); in LowerBUILD_VECTOR()
2275 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VecT, Result, Lane, in LowerBUILD_VECTOR()