Lines Matching refs:VE
85 addRegisterClass(MVT::i32, &VE::I32RegClass); in initRegisterClasses()
86 addRegisterClass(MVT::i64, &VE::I64RegClass); in initRegisterClasses()
87 addRegisterClass(MVT::f32, &VE::F32RegClass); in initRegisterClasses()
88 addRegisterClass(MVT::f64, &VE::I64RegClass); in initRegisterClasses()
89 addRegisterClass(MVT::f128, &VE::F128RegClass); in initRegisterClasses()
93 addRegisterClass(VecVT, &VE::V64RegClass); in initRegisterClasses()
94 addRegisterClass(MVT::v256i1, &VE::VMRegClass); in initRegisterClasses()
95 addRegisterClass(MVT::v512i1, &VE::VM512RegClass); in initRegisterClasses()
415 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerReturn()
493 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerFormalArguments()
560 .Case("sp", VE::SX11) // Stack pointer in getRegisterByName()
561 .Case("fp", VE::SX9) // Frame pointer in getRegisterByName()
562 .Case("sl", VE::SX8) // Stack limit in getRegisterByName()
563 .Case("lr", VE::SX10) // Link register in getRegisterByName()
564 .Case("tp", VE::SX14) // Thread pointer in getRegisterByName()
565 .Case("outer", VE::SX12) // Outer regiser in getRegisterByName()
566 .Case("info", VE::SX17) // Info area register in getRegisterByName()
567 .Case("got", VE::SX15) // Global offset table register in getRegisterByName()
568 .Case("plt", VE::SX16) // Procedure linkage table register in getRegisterByName()
684 RegsToPass.push_back(std::make_pair(VE::SX12, Callee)); in LowerCall()
715 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerCall()
733 SDValue StackPtr = DAG.getRegister(VE::SX11, PtrVT); in LowerCall()
840 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerCall()
913 setStackPointerRegisterToSaveRestore(VE::SX11); in VETargetLowering()
1120 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1126 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1135 return SDValue(DAG.getMachineNode(VE::FENCEM, DL, MVT::Other, in lowerATOMIC_FENCE()
1294 Chain = DAG.getCopyFromReg(Chain, DL, VE::SX0, PtrVT, Chain.getValue(1)); in lowerToTLSGeneralDynamicModel()
1346 SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32); in lowerLoadF128()
1347 SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32); in lowerLoadF128()
1395 VM = DAG.getMachineNode(VE::LVMir_m, DL, MVT::i64, in lowerLoadI1()
1416 VM = DAG.getMachineNode(VE::LVMyir_y, DL, MVT::i64, in lowerLoadI1()
1458 SDValue SubRegEven = DAG.getTargetConstant(VE::sub_even, DL, MVT::i32); in lowerStoreF128()
1459 SDValue SubRegOdd = DAG.getTargetConstant(VE::sub_odd, DL, MVT::i32); in lowerStoreF128()
1509 DAG.getMachineNode(VE::SVMmi, DL, MVT::i64, StNode->getValue(), in lowerStoreI1()
1524 DAG.getMachineNode(VE::SVMyi, DL, MVT::i64, StNode->getValue(), in lowerStoreI1()
1578 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(VE::SX9, PtrVT), in lowerVASTART()
2030 const TargetRegisterClass *RC = &VE::I64RegClass; in prepareMBB()
2040 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2044 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2047 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result) in prepareMBB()
2048 .addReg(VE::SX15) in prepareMBB()
2056 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2060 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2063 BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result) in prepareMBB()
2080 const TargetRegisterClass *RC = &VE::I64RegClass; in prepareSymbol()
2092 BuildMI(MBB, I, DL, TII->get(VE::GETFUNPLT), Result) in prepareSymbol()
2101 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2105 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2108 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result) in prepareSymbol()
2109 .addReg(VE::SX15) in prepareSymbol()
2121 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2125 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2128 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3) in prepareSymbol()
2129 .addReg(VE::SX15) in prepareSymbol()
2132 BuildMI(MBB, I, DL, TII->get(VE::LDrii), Result) in prepareSymbol()
2144 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2148 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2151 BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result) in prepareSymbol()
2171 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in setupEntryBlockForSjLj()
2243 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in emitEHSjLjSetJmp()
2247 MIB.addReg(VE::SX17); in emitEHSjLjSetJmp()
2252 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in emitEHSjLjSetJmp()
2263 BuildMI(*ThisMBB, MI, DL, TII->get(VE::EH_SjLj_Setup)).addMBB(RestoreMBB); in emitEHSjLjSetJmp()
2271 BuildMI(MainMBB, DL, TII->get(VE::LEAzii), MainDestReg) in emitEHSjLjSetJmp()
2278 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg) in emitEHSjLjSetJmp()
2290 BuildMI(RestoreMBB, DL, TII->get(VE::LDrii), VE::SX17); in emitEHSjLjSetJmp()
2291 MIB.addReg(VE::SX10); in emitEHSjLjSetJmp()
2296 BuildMI(RestoreMBB, DL, TII->get(VE::LEAzii), RestoreDestReg) in emitEHSjLjSetJmp()
2300 BuildMI(RestoreMBB, DL, TII->get(VE::BRCFLa_t)).addMBB(SinkMBB); in emitEHSjLjSetJmp()
2320 Register Tmp = MRI.createVirtualRegister(&VE::I64RegClass); in emitEHSjLjLongJmp()
2322 Register FP = VE::SX9; in emitEHSjLjLongJmp()
2323 Register SP = VE::SX11; in emitEHSjLjLongJmp()
2339 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), FP); in emitEHSjLjLongJmp()
2346 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), Tmp); in emitEHSjLjLongJmp()
2354 BuildMI(*ThisMBB, MI, DL, TII->get(VE::ORri), VE::SX10) in emitEHSjLjLongJmp()
2359 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), SP); in emitEHSjLjLongJmp()
2366 BuildMI(*ThisMBB, MI, DL, TII->get(VE::BCFLari_t)) in emitEHSjLjLongJmp()
2472 BuildMI(TrapBB, DL, TII->get(VE::BSICrii), VE::SX10) in emitSjLjDispatchBlock()
2489 BuildMI(DispatchBB, DL, TII->get(VE::NOP)) in emitSjLjDispatchBlock()
2495 BuildMI(DispatchBB, DL, TII->get(VE::GETGOT), VE::SX15); in emitSjLjDispatchBlock()
2499 const TargetRegisterClass *RC = &VE::I64RegClass; in emitSjLjDispatchBlock()
2501 addFrameReference(BuildMI(DispatchBB, DL, TII->get(VE::LDLZXrii), IReg), FI, in emitSjLjDispatchBlock()
2504 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLir_t)) in emitSjLjDispatchBlock()
2512 BuildMI(DispatchBB, DL, TII->get(VE::LEAzii), TmpReg) in emitSjLjDispatchBlock()
2516 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLrr_t)) in emitSjLjDispatchBlock()
2532 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2536 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2) in emitSjLjDispatchBlock()
2539 BuildMI(DispContBB, DL, TII->get(VE::LEASLrri), BReg) in emitSjLjDispatchBlock()
2540 .addReg(VE::SX15) in emitSjLjDispatchBlock()
2548 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2552 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2) in emitSjLjDispatchBlock()
2555 BuildMI(DispContBB, DL, TII->get(VE::LEASLrii), BReg) in emitSjLjDispatchBlock()
2571 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2574 BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg) in emitSjLjDispatchBlock()
2578 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t)) in emitSjLjDispatchBlock()
2597 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2600 BuildMI(DispContBB, DL, TII->get(VE::LDLZXrri), OReg) in emitSjLjDispatchBlock()
2607 BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg) in emitSjLjDispatchBlock()
2610 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t)) in emitSjLjDispatchBlock()
2684 case VE::EH_SjLj_LongJmp: in EmitInstrWithCustomInserter()
2686 case VE::EH_SjLj_SetJmp: in EmitInstrWithCustomInserter()
2688 case VE::EH_SjLj_Setup_Dispatch: in EmitInstrWithCustomInserter()
3023 SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32); in combineTRUNCATE()
3072 RC = &VE::I64RegClass; in getRegForInlineAsmConstraint()
3075 RC = &VE::V64RegClass; in getRegForInlineAsmConstraint()
3143 SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0); in lowerEXTRACT_VECTOR_ELT()
3151 SDValue SubI32 = DAG.getTargetConstant(VE::sub_i32, DL, MVT::i32); in lowerEXTRACT_VECTOR_ELT()
3201 SDValue(DAG.getMachineNode(VE::LVSvr, DL, MVT::i64, {Vec, HalfIdx}), 0); in lowerINSERT_VECTOR_ELT()
3212 SDValue(DAG.getMachineNode(VE::LSVrr_v, DL, Vec.getSimpleValueType(), in lowerINSERT_VECTOR_ELT()