Lines Matching refs:MachineBasicBlock
142 MachineBasicBlock *getMBBTarget() { in getMBBTarget()
175 MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB);
178 MachineBasicBlock *splitBlockAfter(MachineBasicBlock::iterator MI,
179 MachineBasicBlock *MBB);
181 MachineBasicBlock *splitBlockBefore(MachineBasicBlock::iterator MI,
182 MachineBasicBlock *MBB);
189 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
190 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
204 emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
237 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
238 MachineBasicBlock *&FBB,
241 unsigned removeBranch(MachineBasicBlock &MBB,
243 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
244 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
250 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
253 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
260 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
263 bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
265 MachineBasicBlock &FMBB,
268 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
272 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
275 void storeRegToStackSlot(MachineBasicBlock &MBB,
276 MachineBasicBlock::iterator MBBI, Register SrcReg,
281 void loadRegFromStackSlot(MachineBasicBlock &MBB,
282 MachineBasicBlock::iterator MBBI, Register DestReg,
291 MachineBasicBlock::iterator InsertPt, int FrameIndex,
296 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
352 bool prepareCompareSwapOperands(MachineBasicBlock::iterator MBBI) const;
360 void loadImmediate(MachineBasicBlock &MBB,
361 MachineBasicBlock::iterator MBBI,