Lines Matching refs:cond4

2305   : InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
2307 [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
2325 : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
2343 : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
2363 (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2382 : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1,
2409 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2436 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2464 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2491 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2518 (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2547 (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2576 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
2918 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3090 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3094 cond4:$valid, cond4:$M3))]> {
3509 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
3512 cond4:$valid, cond4:$M3))]> {
3555 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
3558 cond4:$valid, cond4:$M4))]> {
3622 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3625 cond4:$valid, cond4:$M3))]> {
5155 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
5195 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
5197 cond4:$valid, cond4:$M3))]> {
5212 (ins cls3:$R3, cls2:$R2, cond4:$valid, cond4:$M4),
5214 cond4:$valid, cond4:$M4))]> {
5226 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
5228 cond4:$valid, cond4:$M3))]> {
5240 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3),
5243 cond4:$valid, cond4:$R3))]> {
5260 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> {