Lines Matching refs:cls
2243 class InherentRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2245 : InstRRE<opcode, (outs cls:$R1), (ins),
2247 [(set cls:$R1, (operator))]> {
2251 class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2252 : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
2408 RegisterOperand cls, ImmOpWithPattern imm>
2409 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2413 RegisterOperand cls, ImmOpWithPattern imm>
2414 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2418 RegisterOperand cls, ImmOpWithPattern imm>
2419 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
2427 RegisterOperand cls, ImmOpWithPattern imm> {
2429 def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
2430 def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
2434 RegisterOperand cls>
2436 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2440 RegisterOperand cls>
2442 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
2446 RegisterOperand cls>
2447 : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
2455 RegisterOperand cls> {
2457 def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
2458 def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
2462 RegisterOperand cls, ImmOpWithPattern imm>
2464 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2468 RegisterOperand cls, ImmOpWithPattern imm>
2470 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
2474 RegisterOperand cls, ImmOpWithPattern imm>
2475 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
2483 RegisterOperand cls, ImmOpWithPattern imm> {
2485 def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
2486 def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
2490 RegisterOperand cls>
2491 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2495 RegisterOperand cls>
2496 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2500 RegisterOperand cls> {
2502 def "" : CmpBranchRRFc<mnemonic, opcode, cls>;
2503 def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
2507 RegisterOperand cls>
2508 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
2516 RegisterOperand cls>
2518 (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2522 RegisterOperand cls>
2524 (ins cls:$R1, cls:$R2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
2528 RegisterOperand cls>
2530 (ins cls:$R1, cls:$R2, (bdaddr12only $B4, $D4):$BD4),
2538 RegisterOperand cls> {
2540 def "" : CmpBranchRRS<mnemonic, opcode, cls>;
2541 def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
2545 RegisterOperand cls, ImmOpWithPattern imm>
2547 (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2551 RegisterOperand cls, ImmOpWithPattern imm>
2553 (ins cls:$R1, imm:$I2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
2557 RegisterOperand cls, ImmOpWithPattern imm>
2559 (ins cls:$R1, imm:$I2, (bdaddr12only $B4, $D4):$BD4),
2567 RegisterOperand cls, ImmOpWithPattern imm> {
2569 def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
2570 def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
2574 RegisterOperand cls>
2576 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
2580 RegisterOperand cls>
2582 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
2586 RegisterOperand cls> {
2588 def "" : CmpBranchRSYb<mnemonic, opcode, cls>;
2589 def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
2593 RegisterOperand cls>
2594 : InstRSYb<opcode, (outs), (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2),
2601 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
2602 : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
2608 class BranchUnaryRIL<string mnemonic, bits<12> opcode, RegisterOperand cls>
2609 : InstRILb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget32:$RI2),
2615 class BranchUnaryRR<string mnemonic, bits<8> opcode, RegisterOperand cls>
2616 : InstRR<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2622 class BranchUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
2623 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src, GR64:$R2),
2629 class BranchUnaryRX<string mnemonic, bits<8> opcode, RegisterOperand cls>
2630 : InstRXa<opcode, (outs cls:$R1),
2631 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2637 class BranchUnaryRXY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2638 : InstRXYa<opcode, (outs cls:$R1),
2639 (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2645 class BranchBinaryRSI<string mnemonic, bits<8> opcode, RegisterOperand cls>
2646 : InstRSI<opcode, (outs cls:$R1), (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2652 class BranchBinaryRIEe<string mnemonic, bits<16> opcode, RegisterOperand cls>
2653 : InstRIEe<opcode, (outs cls:$R1),
2654 (ins cls:$R1src, cls:$R3, brtarget16:$RI2),
2660 class BranchBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls>
2661 : InstRSa<opcode, (outs cls:$R1),
2662 (ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2),
2668 class BranchBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls>
2670 (outs cls:$R1),
2671 (ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2),
2677 class LoadMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2679 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2684 class LoadMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2686 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2692 bits<16> rsyOpcode, RegisterOperand cls> {
2693 let DispKey = mnemonic # cls in {
2695 def "" : LoadMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2697 def Y : LoadMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2701 class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
2702 : InstSSe<opcode, (outs cls:$R1, cls:$R3),
2721 RegisterOperand cls>
2722 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
2724 [(operator cls:$R1, pcrel32:$RI2)]> {
2733 RegisterOperand cls, bits<5> bytes,
2735 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2737 [(operator cls:$R1, mode:$XBD2)]> {
2738 let OpKey = mnemonic#"r"#cls;
2745 RegisterOperand cls, bits<5> bytes,
2747 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2749 [(operator cls:$R1, mode:$XBD2)]> {
2750 let OpKey = mnemonic#"r"#cls;
2757 SDPatternOperator operator, RegisterOperand cls,
2759 let DispKey = mnemonic # cls in {
2761 def "" : StoreRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
2763 def Y : StoreRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
2830 class StoreMultipleRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
2832 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2837 class StoreMultipleRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
2839 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2845 bits<16> rsyOpcode, RegisterOperand cls> {
2846 let DispKey = mnemonic # cls in {
2848 def "" : StoreMultipleRS<mnemonic, rsOpcode, cls, bdaddr12pair>;
2850 def Y : StoreMultipleRSY<mnemonic#"y", rsyOpcode, cls, bdaddr20pair>;
2915 RegisterOperand cls, bits<5> bytes,
2918 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
2928 RegisterOperand cls, bits<5> bytes,
2930 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3),
2938 RegisterOperand cls, bits<5> bytes,
2940 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2),
2950 RegisterOperand cls, bits<5> bytes,
2953 def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2954 def Asm : AsmCondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
2961 class SideEffectUnaryRR<string mnemonic, bits<8>opcode, RegisterOperand cls>
2962 : InstRR<opcode, (outs), (ins cls:$R1),
2967 class SideEffectUnaryRRE<string mnemonic, bits<16> opcode, RegisterOperand cls,
2969 : InstRRE<opcode, (outs), (ins cls:$R1),
2970 mnemonic#"\t$R1", [(operator cls:$R1)]> {
3045 class UnaryTiedRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
3046 : InstRRE<opcode, (outs cls:$R1), (ins cls:$R1src),
3063 RegisterOperand cls, ImmOpWithPattern imm>
3064 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
3066 [(set cls:$R1, (operator imm:$I2))]>;
3069 RegisterOperand cls, ImmOpWithPattern imm>
3070 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
3072 [(set cls:$R1, (operator imm:$I2))]>;
3075 RegisterOperand cls>
3076 : InstRILb<opcode, (outs cls:$R1), (ins pcrel32:$RI2),
3078 [(set cls:$R1, (operator pcrel32:$RI2))]> {
3087 SDPatternOperator operator, RegisterOperand cls,
3089 : InstRSYb<opcode, (outs cls:$R1),
3090 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3092 [(set cls:$R1,
3093 (z_select_ccmask (operator bdaddr20only:$BD2), cls:$R1src,
3100 let OpKey = mnemonic#"r"#cls;
3102 let MemKey = mnemonic#cls;
3109 RegisterOperand cls, bits<5> bytes,
3111 : InstRSYb<opcode, (outs cls:$R1),
3112 (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3),
3122 RegisterOperand cls, bits<5> bytes,
3124 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2),
3137 RegisterOperand cls, bits<5> bytes,
3140 def "" : CondUnaryRSY<mnemonic, opcode, operator, cls, bytes, mode>;
3141 def Asm : AsmCondUnaryRSY<mnemonic, opcode, cls, bytes, mode>;
3145 RegisterOperand cls, bits<5> bytes,
3147 : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3149 [(set cls:$R1, (operator mode:$XBD2))]> {
3150 let OpKey = mnemonic#"r"#cls;
3157 RegisterOperand cls, bits<5> bytes>
3158 : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3160 [(set cls:$R1, (operator bdxaddr12only:$XBD2))]> {
3161 let OpKey = mnemonic#"r"#cls;
3169 RegisterOperand cls, bits<5> bytes,
3171 : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3173 [(set cls:$R1, (operator mode:$XBD2))]> {
3174 let OpKey = mnemonic#"r"#cls;
3181 SDPatternOperator operator, RegisterOperand cls,
3183 let DispKey = mnemonic # cls in {
3185 def "" : UnaryRX<mnemonic, rxOpcode, operator, cls, bytes, bdxaddr12pair>;
3187 def Y : UnaryRXY<mnemonic#"y", rxyOpcode, operator, cls, bytes,
3293 RegisterOperand cls>
3294 : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3298 RegisterOperand cls>
3299 : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
3303 RegisterOperand cls>
3304 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
3427 let OpKey = mnemonic#cls;
3593 RegisterOperand cls, ImmOpWithPattern imm>
3594 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3596 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3602 RegisterOperand cls, ImmOpWithPattern imm>
3603 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3605 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3608 SDPatternOperator operator, RegisterOperand cls,
3612 def K : BinaryRIE<mnemonic#"k", opcode2, operator, cls, imm>,
3615 def "" : BinaryRI<mnemonic, opcode1, operator, cls, imm>;
3619 class CondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3621 : InstRIEg<opcode, (outs cls:$R1),
3622 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3624 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
3633 class AsmCondBinaryRIE<string mnemonic, bits<16> opcode, RegisterOperand cls,
3635 : InstRIEg<opcode, (outs cls:$R1),
3636 (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
3644 RegisterOperand cls, ImmOpWithPattern imm>
3645 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3655 RegisterOperand cls, ImmOpWithPattern imm> {
3657 def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
3658 def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;
3662 RegisterOperand cls, ImmOpWithPattern imm>
3663 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3665 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3671 RegisterOperand cls>
3672 : InstRSa<opcode, (outs cls:$R1),
3673 (ins cls:$R1src, (shift12only $B2, $D2):$BD2),
3675 [(set cls:$R1, (operator cls:$R1src, shift12only:$BD2))]> {
3682 RegisterOperand cls>
3683 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2),
3685 [(set cls:$R1, (operator cls:$R3, shift20only:$BD2))]>;
3688 SDPatternOperator operator, RegisterOperand cls> {
3691 def K : BinaryRSY<mnemonic#"k", opcode2, operator, cls>,
3694 def "" : BinaryRS<mnemonic, opcode1, operator, cls>;
3698 class BinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
3699 : InstRSLb<opcode, (outs cls:$R1),
3706 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3708 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3710 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3711 let OpKey = mnemonic#"r"#cls;
3720 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
3721 : InstRXE<opcode, (outs cls:$R1),
3722 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3724 [(set cls:$R1, (operator cls:$R1src,
3726 let OpKey = mnemonic#"r"#cls;
3742 let OpKey = mnemonic#"r"#cls;
3749 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
3751 : InstRXYa<opcode, (outs cls:$R1),
3752 (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3754 [(set cls:$R1, (operator cls:$R1src, (load mode:$XBD2)))]> {
3755 let OpKey = mnemonic#"r"#cls;
3764 SDPatternOperator operator, RegisterOperand cls,
3766 let DispKey = mnemonic # cls in {
3768 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
3771 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load, bytes,
3797 let DispKey = mnemonic # cls in {
3805 class BinarySSF<string mnemonic, bits<12> opcode, RegisterOperand cls>
3806 : InstSSF<opcode, (outs cls:$R3),
4003 class BinaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4004 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
4074 class StoreBinaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4076 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4082 class StoreBinaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4084 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4091 bits<16> rsyOpcode, RegisterOperand cls,
4093 let DispKey = mnemonic # cls in {
4095 def "" : StoreBinaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
4097 def Y : StoreBinaryRSY<mnemonic#"y", rsyOpcode, cls, bytes,
4102 class StoreBinaryRSL<string mnemonic, bits<16> opcode, RegisterOperand cls>
4104 (ins cls:$R1, (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2,
4141 RegisterOperand cls>
4144 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
4168 RegisterOperand cls, ImmOpWithPattern imm>
4169 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
4171 [(set CC, (operator cls:$R1, imm:$I2))]> {
4176 RegisterOperand cls, ImmOpWithPattern imm>
4177 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
4179 [(set CC, (operator cls:$R1, imm:$I2))]> {
4184 RegisterOperand cls, SDPatternOperator load>
4185 : InstRILb<opcode, (outs), (ins cls:$R1, pcrel32:$RI2),
4187 [(set CC, (operator cls:$R1, (load pcrel32:$RI2)))]> {
4197 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
4199 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4201 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
4202 let OpKey = mnemonic#"r"#cls;
4210 RegisterOperand cls, SDPatternOperator load, bits<5> bytes>
4211 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4213 [(set CC, (operator cls:$R1, (load bdxaddr12only:$XBD2)))]> {
4214 let OpKey = mnemonic#"r"#cls;
4223 RegisterOperand cls, SDPatternOperator load, bits<5> bytes,
4225 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4227 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
4228 let OpKey = mnemonic#"r"#cls;
4236 SDPatternOperator operator, RegisterOperand cls,
4238 let DispKey = mnemonic # cls in {
4240 def "" : CompareRX<mnemonic, rxOpcode, operator, cls,
4243 def Y : CompareRXY<mnemonic#"y", rxyOpcode, operator, cls,
4248 class CompareRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4250 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4256 class CompareRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4258 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4265 RegisterOperand cls, bits<5> bytes> {
4266 let DispKey = mnemonic # cls in {
4268 def "" : CompareRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
4270 def Y : CompareRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
4367 RegisterOperand cls>
4368 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4370 [(set CC, (operator cls:$R1, bdxaddr12only:$XBD2))]> {
4465 RegisterOperand cls>
4468 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
4498 let OpKey = mnemonic#cls;
4504 class TernaryRS<string mnemonic, bits<8> opcode, RegisterOperand cls,
4506 : InstRSb<opcode, (outs cls:$R1),
4507 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4516 class TernaryRSY<string mnemonic, bits<16> opcode, RegisterOperand cls,
4518 : InstRSYb<opcode, (outs cls:$R1),
4519 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4529 RegisterOperand cls, bits<5> bytes> {
4530 let DispKey = mnemonic # cls in {
4532 def "" : TernaryRS<mnemonic, rsOpcode, cls, bytes, bdaddr12pair>;
4534 def Y : TernaryRSY<mnemonic#"y", rsyOpcode, cls, bytes, bdaddr20pair>;
4576 let OpKey = mnemonic#"r"#cls;
4605 class TernaryVRIi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4607 (ins cls:$R2, imm32zx8:$I3, imm32zx4:$M4),
4770 TypedReg tr1, TypedReg tr2, RegisterOperand cls, bits<4> type>
4772 (ins tr2.op:$V1src, cls:$R3, (shift12only $B2, $D2):$BD2),
4775 cls:$R3,
4782 class TernaryVRRi<string mnemonic, bits<16> opcode, RegisterOperand cls>
4783 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4942 RegisterOperand cls>
4944 (ins cls:$R1, (bdaddr12only $B2, $D2):$BD2, cls:$R3,
4949 RegisterOperand cls, AddressingMode mode = bdaddr20only>
4950 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2),
4952 [(set cls:$R1, (operator mode:$BD2, cls:$R3))]> {
4968 RegisterOperand cls, AddressingMode mode = bdaddr12only>
4969 : InstRSa<opcode, (outs cls:$R1),
4970 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
4972 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4980 RegisterOperand cls, AddressingMode mode = bdaddr20only>
4981 : InstRSYa<opcode, (outs cls:$R1),
4982 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
4984 [(set cls:$R1, (operator mode:$BD2, cls:$R1src, cls:$R3))]> {
4992 SDPatternOperator operator, RegisterOperand cls> {
4993 let DispKey = mnemonic # cls in {
4995 def "" : CmpSwapRS<mnemonic, rsOpcode, operator, cls, bdaddr12pair>;
4997 def Y : CmpSwapRSY<mnemonic#"y", rsyOpcode, operator, cls, bdaddr20pair>;
5056 class UnaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
5058 : Pseudo<(outs cls:$R1), (ins imm:$I2),
5059 [(set cls:$R1, (operator imm:$I2))]>;
5063 RegisterOperand cls, bits<5> bytes,
5065 : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
5066 [(set cls:$R1, (operator mode:$XBD2))]> {
5067 let OpKey = key#"r"#cls;
5085 class BinaryRIPseudo<SDPatternOperator operator, RegisterOperand cls,
5087 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
5088 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5093 class BinaryRIEPseudo<SDPatternOperator operator, RegisterOperand cls,
5095 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
5096 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
5100 RegisterOperand cls, ImmOpWithPattern imm> {
5103 def K : BinaryRIEPseudo<operator, cls, imm>,
5106 def "" : BinaryRIPseudo<operator, cls, imm>,
5115 class MemFoldPseudo<string mnemonic, RegisterOperand cls, bits<5> bytes,
5117 : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> {
5120 mnemonic#"rk"#cls));
5122 let MemKey = mnemonic#cls;
5131 class MemFoldPseudo_FP<string mnemonic, RegisterOperand cls, bits<5> bytes,
5133 : MemFoldPseudo<mnemonic, cls, bytes, mode> {
5134 let OpKey = mnemonic#"r"#"MemFold"#cls;
5137 class MemFoldPseudo_FPTern<string mnemonic, RegisterOperand cls, bits<5> bytes,
5139 : Pseudo<(outs cls:$R1),
5140 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
5141 let OpKey = mnemonic#"r"#"MemFold"#cls;
5143 let MemKey = mnemonic#cls;
5152 class MemFoldPseudo_CondMove<string mnemonic, RegisterOperand cls, bits<5> bytes,
5154 : Pseudo<(outs cls:$R1),
5155 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
5156 let OpKey = !subst("loc", "sel", mnemonic)#"r"#cls;
5158 let MemKey = mnemonic#cls;
5166 class CompareRIPseudo<SDPatternOperator operator, RegisterOperand cls,
5168 : Pseudo<(outs), (ins cls:$R1, imm:$I2),
5169 [(set CC, (operator cls:$R1, imm:$I2))]> {
5174 class CompareRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
5177 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5178 [(set CC, (operator cls:$R1, (load mode:$XBD2)))]> {
5224 class CondBinaryRIEPseudo<RegisterOperand cls, ImmOpWithPattern imm>
5225 : Pseudo<(outs cls:$R1),
5226 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
5227 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
5237 RegisterOperand cls, bits<5> bytes,
5239 : Pseudo<(outs cls:$R1),
5240 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3),
5241 [(set cls:$R1,
5242 (z_select_ccmask (operator mode:$BD2), cls:$R1src,
5249 let OpKey = mnemonic#"r"#cls;
5251 let MemKey = mnemonic#cls;
5257 class CondStoreRSYPseudo<RegisterOperand cls, bits<5> bytes,
5260 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> {
5267 class StoreRXYPseudo<SDPatternOperator operator, RegisterOperand cls,
5269 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5270 [(operator cls:$R1, mode:$XBD2)]> {
5290 class SelectWrapper<ValueType vt, RegisterOperand cls>
5291 : Pseudo<(outs cls:$dst),
5292 (ins cls:$src1, cls:$src2, imm32zx4:$valid, imm32zx4:$cc),
5293 [(set (vt cls:$dst), (z_select_ccmask cls:$src1, cls:$src2,
5301 multiclass CondStores<RegisterOperand cls, SDPatternOperator store,
5306 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
5307 [(store (z_select_ccmask cls:$new, (load mode:$addr),
5311 (ins cls:$new, mode:$addr, imm32zx4:$valid, imm32zx4:$cc),
5312 [(store (z_select_ccmask (load mode:$addr), cls:$new,
5372 class BinaryAliasRI<SDPatternOperator operator, RegisterOperand cls,
5374 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5375 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5380 class BinaryAliasRIL<SDPatternOperator operator, RegisterOperand cls,
5382 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5383 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5388 class BinaryAliasVRRf<RegisterOperand cls>
5389 : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;
5392 class CompareAliasRI<SDPatternOperator operator, RegisterOperand cls,
5394 : Alias<4, (outs), (ins cls:$R1, imm:$I2),
5395 [(set CC, (operator cls:$R1, imm:$I2))]> {
5422 SDPatternOperator operator, RegisterOperand cls,
5425 def "" : BinaryRXY<mnemonic, opcode, operator, cls, load, bytes, mode> {
5426 let MemKey = mnemonic#cls;
5430 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, mode>;
5435 RegisterOperand cls,
5437 let DispKey = mnemonic # cls in {
5438 def "" : BinaryRX<mnemonic, rxOpcode, operator, cls, load, bytes,
5441 let MemKey = mnemonic#cls;
5445 def Y : BinaryRXY<mnemonic#"y", rxyOpcode, operator, cls, load,
5448 def _MemFoldPseudo : MemFoldPseudo<mnemonic, cls, bytes, bdxaddr12pair>;
5452 SDPatternOperator operator, RegisterOperand cls,
5454 def "" : BinaryRXE<mnemonic, opcode, operator, cls, load, bytes> {
5455 let MemKey = mnemonic#cls;
5458 def _MemFoldPseudo : MemFoldPseudo_FP<mnemonic, cls, bytes, bdxaddr12pair>;
5474 RegisterOperand cls, bits<5> bytes,
5476 defm "" : CondUnaryRSYPair<mnemonic, opcode, operator, cls, bytes, mode>;
5477 def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>;
5482 RegisterOperand cls, bits<5> bytes,
5484 def "" : CondUnaryRSYPseudo<mnemonic, operator, cls, bytes, mode>;
5485 def _MemFoldPseudo : MemFoldPseudo_CondMove<mnemonic, cls, bytes, mode>;