Lines Matching refs:X2
618 bits<4> X2;
624 let Inst{19-16} = X2;
637 bits<4> X2;
643 let Inst{19-16} = X2;
656 bits<4> X2;
663 let Inst{35-32} = X2;
680 bits<4> X2;
686 let Inst{35-32} = X2;
702 bits<4> X2;
708 let Inst{35-32} = X2;
724 bits<4> X2;
730 let Inst{35-32} = X2;
1722 bits<4> X2;
1729 let Inst{35-32} = X2;
2300 : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2363 (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2370 (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2374 : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2383 (bdxaddr20only $B2, $D2, $X2):$XBD2),
2391 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2398 : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2),
2631 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2639 (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2735 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2747 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2771 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2781 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2789 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
2794 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3001 : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3007 : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3147 : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3158 : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3171 : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3265 : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3275 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3283 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3287 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3294 : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3299 : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
3708 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3722 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3739 (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3752 (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
4066 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
4133 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4199 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4211 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4225 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4368 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4572 (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4815 (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
5013 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
5065 : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
5117 : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> {
5140 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
5177 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5269 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5362 : Alias<6, (outs tr.op:$V1), (ins (mode $B2, $D2, $X2):$XBD2),
5368 : Alias<6, (outs), (ins tr.op:$V1, (mode $B2, $D2, $X2):$XBD2),