Lines Matching refs:VR128

2256   : InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
2710     def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2714       def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2781             (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2789                         (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
2794                        (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2802              (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2804              [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2813              (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2815              [(operator VR128:$V1, GR32:$R3, bdaddr12only:$BD2)]> {
2823             (ins VR128:$V1, (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
2825             [(operator VR128:$V1, imm32zx8:$I3, bdaddr12only:$BD2)]> {
2856     def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2861       def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
3201   : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
3219   : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3226   : InstVRRa<opcode, (outs VR128:$V1),
3227              (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
3255     def "" : InstVRRa<opcode, (outs VR128:$V1),
3256                      (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
3259                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2,
3274   : InstVRX<opcode, (outs VR128:$V1),
3282     def Align : InstVRX<opcode, (outs VR128:$V1),
3286       def "" : InstVRX<opcode, (outs VR128:$V1),
3821   : InstVRIb<opcode, (outs VR128:$V1),
3835   : InstVRIc<opcode, (outs VR128:$V1),
3836              (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3850   : InstVRIe<opcode, (outs VR128:$V1),
3851              (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5),
3855   : InstVRIh<opcode, (outs VR128:$V1),
3870   : InstVRRa<opcode, (outs VR128:$V1),
3871              (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3886   : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
3892   : InstVRRb<opcode, (outs VR128:$V1),
3893              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3910   : InstVRRb<opcode, (outs VR128:$V1),
3911              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3939     def "" : InstVRRb<opcode, (outs VR128:$V1),
3940                      (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3943                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3963   : InstVRRc<opcode, (outs VR128:$V1),
3964              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
3971   : InstVRRc<opcode, (outs VR128:$V1),
3972              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3992   : InstVRRc<opcode, (outs VR128:$V1),
3993              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4004   : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
4010   : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
4024   : InstVRSa<opcode, (outs VR128:$V1),
4025              (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4),
4030   : InstVRSb<opcode, (outs VR128:$V1),
4033              [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
4050              (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4),
4055   : InstVRSd<opcode, (outs VR128:$V1),
4058              [(set VR128:$V1, (operator GR32:$R3, bdaddr12only:$BD2))]> {
4065   : InstVRX<opcode, (outs VR128:$V1),
4112   : InstVSI<opcode, (outs VR128:$V1),
4115             [(set VR128:$V1, (operator imm32zx8:$I3, bdaddr12only:$BD2))]> {
4123             (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4338   : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4354   : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4387   : InstVRRg<opcode, (outs), (ins VR128:$V1),
4606   : InstVRIi<opcode, (outs VR128:$V1),
4623   : InstVRRa<opcode, (outs VR128:$V1),
4624              (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4663     def "" : InstVRRb<opcode, (outs VR128:$V1),
4664                      (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4667                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4697   : InstVRRc<opcode, (outs VR128:$V1),
4698              (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4715   : InstVRRd<opcode, (outs VR128:$V1),
4716              (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4740     def "" : InstVRRd<opcode, (outs VR128:$V1),
4741                       (ins VR128:$V2, VR128:$V3, VR128:$V4,
4745                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4746                                             VR128:$V4, imm32zx4:$M5, 0)>;
4765   : InstVRRe<opcode, (outs VR128:$V1),
4766              (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4783   : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2,
4788   : InstVRRj<opcode, (outs VR128:$V1), (ins VR128:$V2,
4789                                         VR128:$V3, imm32zx4:$M4),
4793   : InstVRSb<opcode, (outs VR128:$V1),
4794              (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2,
4803   : InstVRV<opcode, (outs VR128:$V1),
4804            (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4841   : InstVRId<opcode, (outs VR128:$V1),
4842              (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4850   : InstVRIf<opcode, (outs VR128:$V1),
4851              (ins VR128:$V2, VR128:$V3,
4856   : InstVRIg<opcode, (outs VR128:$V1),
4857              (ins VR128:$V2, imm32zx8:$I3,
4877   : InstVRRd<opcode, (outs VR128:$V1),
4878              (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4908                   (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4909                                             VR128:$V4, imm32zx4_timm:$M5, 0)>;
5389   : Alias<6, (outs VR128:$V1), (ins cls:$R2, cls:$R3), []>;