Lines Matching refs:V3
1173 bits<5> V3;
1179 let Inst{35-32} = V3{3-0};
1183 let Inst{10} = V3{4};
1195 bits<5> V3;
1202 let Inst{31-28} = V3{3-0};
1208 let Inst{9} = V3{4};
1243 bits<5> V3;
1250 let Inst{31-28} = V3{3-0};
1256 let Inst{9} = V3{4};
1364 bits<5> V3;
1371 let Inst{31-28} = V3{3-0};
1381 let Inst{9} = V3{4};
1393 bits<5> V3;
1401 let Inst{31-28} = V3{3-0};
1408 let Inst{9} = V3{4};
1423 bits<5> V3;
1431 let Inst{31-28} = V3{3-0};
1441 let Inst{9} = V3{4};
1453 bits<5> V3;
1461 let Inst{31-28} = V3{3-0};
1468 let Inst{9} = V3{4};
1562 bits<5> V3;
1568 let Inst{31-28} = V3{3-0};
1575 let Inst{9} = V3{4};
1612 bits<5> V3;
1617 let Inst{35-32} = V3{3-0};
1622 let Inst{10} = V3{4};
1657 bits<5> V3;
1662 let Inst{35-32} = V3{3-0};
1667 let Inst{10} = V3{4};
2710 def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2712 mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
2714 def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
2716 mnemonic#"\t$V1, $V3, $BD2", []>;
2856 def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2859 mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
2861 def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
2863 mnemonic#"\t$V1, $V3, $BD2", []>;
3827 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
3828 mnemonic#"\t$V1, $V3, $I2",
3829 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
3836 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3837 mnemonic#"\t$V1, $V3, $I2, $M4", []>;
3877 : InstVRRb<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3878 mnemonic#"\t$V1, $V2, $V3",
3880 (tr2.vt tr2.op:$V3)))]> {
3886 : InstVRRb<opcode, (outs VR128:$V1), (ins VR128:$V2, VR128:$V3, imm32zx4:$M5),
3887 mnemonic#"\t$V1, $V2, $V3, $M5", []> {
3893 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3894 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3911 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3912 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3926 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M5),
3927 mnemonic#"\t$V1, $V2, $V3, $M5", []>;
3928 def : Pat<(tr1.vt (operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3))),
3929 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, 0)>;
3930 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
3932 tr2.op:$V3, 0)>;
3940 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3941 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
3942 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
3943 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
3950 : InstVRRc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V2, tr2.op:$V3),
3951 mnemonic#"\t$V1, $V2, $V3",
3953 (tr2.vt tr2.op:$V3)))]> {
3964 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4),
3965 mnemonic#"\t$V1, $V2, $V3, $M4", []> {
3972 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
3973 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []> {
3993 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
3995 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4016 (ins tr2.op:$V3, (shift12only $B2, $D2):$BD2),
4017 mnemonic#"\t$V1, $V3, $BD2",
4018 [(set (tr1.vt tr1.op:$V1), (operator (tr2.vt tr2.op:$V3),
4025 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4),
4026 mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
4042 (ins tr.op:$V3, (shift12only $B2, $D2):$BD2),
4043 mnemonic#"\t$R1, $V3, $BD2",
4044 [(set GR64:$R1, (operator (tr.vt tr.op:$V3), shift12only:$BD2))]> {
4050 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4),
4051 mnemonic#"\t$R1, $V3, $BD2, $M4", []>;
4597 (ins tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4598 mnemonic#"\t$V1, $V2, $V3, $I4",
4600 (tr2.vt tr2.op:$V3),
4631 (ins tr2.op:$V2, tr2.op:$V3, m5mask:$M5),
4632 mnemonic#"\t$V1, $V2, $V3, $M5",
4634 (tr2.vt tr2.op:$V3),
4650 def : InstAlias<mnemonic#"\t$V1, $V2, $V3",
4652 tr2.op:$V3, 0)>;
4656 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3",
4658 tr2.op:$V3, 0)>;
4664 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5),
4665 mnemonic#"\t$V1, $V2, $V3, $M4, $M5", []>;
4666 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $M4",
4667 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4674 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M4),
4675 mnemonic#"\t$V1, $V2, $V3, $M4",
4677 (tr2.vt tr2.op:$V3),
4687 (ins tr2.op:$V2, tr2.op:$V3, imm32zx4:$M6),
4688 mnemonic#"\t$V1, $V2, $V3, $M6",
4690 (tr2.vt tr2.op:$V3),
4698 (ins VR128:$V2, VR128:$V3, imm32zx4:$M4, imm32zx4:$M5,
4700 mnemonic#"\t$V1, $V2, $V3, $M4, $M5, $M6", []>;
4705 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4706 mnemonic#"\t$V1, $V2, $V3, $V4",
4708 (tr2.vt tr2.op:$V3),
4716 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5),
4717 mnemonic#"\t$V1, $V2, $V3, $V4, $M5", []> {
4728 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, imm32zx4:$M6),
4729 mnemonic#"\t$V1, $V2, $V3, $V4, $M6", []>;
4730 def : Pat<(operator (tr2.vt tr2.op:$V2), (tr2.vt tr2.op:$V3),
4732 (!cast<Instruction>(NAME) tr2.op:$V2, tr2.op:$V3, tr1.op:$V4, 0)>;
4733 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4735 tr2.op:$V3, tr1.op:$V4, 0)>;
4741 (ins VR128:$V2, VR128:$V3, VR128:$V4,
4743 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4744 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4745 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,
4753 (ins tr2.op:$V2, tr2.op:$V3, tr1.op:$V4),
4754 mnemonic#"\t$V1, $V2, $V3, $V4",
4756 (tr2.vt tr2.op:$V3),
4766 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4767 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4789 VR128:$V3, imm32zx4:$M4),
4790 mnemonic#"\t$V1, $V2, $V3, $M4", []>;
4829 (ins tr2.op:$V1src, tr2.op:$V2, tr2.op:$V3, imm32zx8:$I4),
4830 mnemonic#"\t$V1, $V2, $V3, $I4",
4833 (tr2.vt tr2.op:$V3),
4842 (ins VR128:$V1src, VR128:$V2, VR128:$V3,
4844 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []> {
4851 (ins VR128:$V2, VR128:$V3,
4853 mnemonic#"\t$V1, $V2, $V3, $I4, $M5", []>;
4866 (ins tr2.op:$V2, tr3.op:$V3, tr4.op:$V4, m6mask:$M6),
4867 mnemonic#"\t$V1, $V2, $V3, $V4, $M6",
4869 (tr3.vt tr3.op:$V3),
4878 (ins VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, imm32zx4:$M6),
4879 mnemonic#"\t$V1, $V2, $V3, $V4, $M5, $M6", []>;
4892 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4",
4894 tr2.op:$V3, tr2.op:$V4, 0)>;
4899 def : InstAlias<mnemonic#"s\t$V1, $V2, $V3, $V4",
4901 tr2.op:$V3, tr2.op:$V4, 0)>;
4907 def : InstAlias<mnemonic#"\t$V1, $V2, $V3, $V4, $M5",
4908 (!cast<Instruction>(NAME) VR128:$V1, VR128:$V2, VR128:$V3,