Lines Matching refs:M3
284 bits<4> M3;
290 let Inst{15-12} = M3;
302 bits<4> M3;
309 let Inst{15-12} = M3;
321 bits<4> M3;
326 let Inst{35-32} = M3;
392 bits<4> M3;
397 let Inst{35-32} = M3;
452 bits<4> M3;
458 let Inst{35-32} = M3;
549 bits<4> M3;
552 let Inst{15-12} = M3;
581 bits<4> M3;
585 let Inst{15-12} = M3;
598 bits<4> M3;
607 let Inst{15-12} = M3;
659 bits<4> M3;
666 let Inst{15-12} = M3;
763 bits<4> M3;
769 let Inst{19-16} = M3;
835 bits<4> M3;
842 let Inst{11-8} = M3;
873 bits<4> M3;
879 let Inst{35-32} = M3;
1134 bits<4> M3;
1140 let Inst{15-12} = M3;
1334 bits<4> M3;
1347 let Inst{15-12} = M3;
1516 bits<4> M3;
1523 let Inst{23-20} = M3;
1539 bits<4> M3;
1546 let Inst{23-20} = M3;
1587 bits<4> M3;
1594 let Inst{23-20} = M3;
1702 bits<4> M3;
1709 let Inst{15-12} = M3;
1725 bits<4> M3;
1732 let Inst{15-12} = M3;
1872 let M3 = 0;
2258 let M3 = 0;
2409 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2410 mnemonic#"$M3\t$R1, $I2", []>;
2414 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2415 mnemonic#"\t$R1, $I2, $M3", []>;
2423 let M3 = V.ccmask;
2436 (ins cls:$R1, cls:$R2, cond4:$M3, brtarget16:$RI4),
2437 mnemonic#"$M3\t$R1, $R2, $RI4", []>;
2442 (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
2443 mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
2451 let M3 = V.ccmask;
2464 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2465 mnemonic#"$M3\t$R1, $I2, $RI4", []>;
2470 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
2471 mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
2479 let M3 = V.ccmask;
2491 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, cond4:$M3),
2492 mnemonic#"$M3\t$R1, $R2", []>;
2496 : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2, imm32zx4:$M3),
2497 mnemonic#"\t$R1, $R2, $M3", []>;
2512 let M3 = V.ccmask;
2518 (ins cls:$R1, cls:$R2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2519 mnemonic#"$M3\t$R1, $R2, $BD4", []>;
2524 (ins cls:$R1, cls:$R2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
2525 mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
2534 let M3 = V.ccmask;
2547 (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2548 mnemonic#"$M3\t$R1, $I2, $BD4", []>;
2553 (ins cls:$R1, imm:$I2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
2554 mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
2563 let M3 = V.ccmask;
2576 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
2577 mnemonic#"$M3\t$R1, $BD2", []>;
2582 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
2583 mnemonic#"\t$R1, $M3, $BD2", []>;
2598 let M3 = V.ccmask;
2774 let M3 = type;
2781 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2782 mnemonic#"\t$V1, $XBD2, $M3", []> {
2790 imm32zx4:$M3),
2791 mnemonic#"\t$V1, $XBD2, $M3", []>;
2792 let M3 = 0 in
2918 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
2919 mnemonic#"$M3\t$R1, $BD2", []> {
2930 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3),
2931 mnemonic#"\t$R1, $BD2, $M3", []> {
2946 let M3 = V.ccmask;
3059 let M3 = 0;
3090 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3091 mnemonic#"$M3\t$R1, $BD2",
3094 cond4:$valid, cond4:$M3))]> {
3112 (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3),
3113 mnemonic#"\t$R1, $BD2, $M3", []> {
3132 let M3 = V.ccmask;
3165 let M3 = 0;
3197 let M3 = type;
3201 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
3202 mnemonic#"\t$V1, $I2, $M3", []>;
3210 let M3 = type;
3219 : InstVRRa<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
3220 mnemonic#"\t$V1, $V2, $M3", []> {
3227 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4),
3228 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
3240 let M3 = type, M4 = 0 in
3256 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M5),
3257 mnemonic#"\t$V1, $V2, $M3, $M5", []>;
3258 def : InstAlias<mnemonic#"\t$V1, $V2, $M3",
3260 imm32zx4:$M3, 0)>;
3268 let M3 = type;
3275 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3276 mnemonic#"\t$V1, $XBD2, $M3", []> {
3283 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3284 mnemonic#"\t$V1, $XBD2, $M3", []>;
3285 let M3 = 0 in
3329 let M3 = 0;
3397 let M3 = 0;
3477 : InstRRFc<opcode, (outs cls1:$R1), (ins cls2:$R2, imm32zx4:$M3),
3478 mnemonic#"\t$R1, $R2, $M3", []>;
3482 : InstRRFc<opcode, (outs cls2:$R2, cls1:$R1), (ins cls1:$R1src, imm:$M3),
3483 mnemonic#"\t$R1, $R2, $M3", []> {
3501 : InstRRFe<opcode, (outs cls1:$R1), (ins imm32zx4:$M3, cls2:$R2),
3502 mnemonic#"\t$R1, $M3, $R2", []> {
3509 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
3510 mnemonic#"$M3\t$R1, $R2",
3512 cond4:$valid, cond4:$M3))]> {
3527 (ins cls1:$R1src, cls2:$R2, imm32zx4:$M3),
3528 mnemonic#"\t$R1, $R2, $M3", []> {
3542 let M3 = V.ccmask;
3622 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3623 mnemonic#"$M3\t$R1, $I2",
3625 cond4:$valid, cond4:$M3))]> {
3636 (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
3637 mnemonic#"\t$R1, $I2, $M3", []> {
3651 let M3 = V.ccmask;
3700 (ins (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
3701 mnemonic#"\t$R1, $BDL2, $M3", []> {
3732 let M3 = 0;
3865 let M3 = type;
3871 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
3872 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
4004 : InstVRRi<opcode, (outs cls:$R1), (ins VR128:$V2, imm32zx4:$M3),
4005 mnemonic#"\t$R1, $V2, $M3", []> {
4010 : InstVRRk<opcode, (outs VR128:$V1), (ins VR128:$V2, imm32zx4:$M3),
4011 mnemonic#"\t$V1, $V2, $M3", []>;
4066 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
4067 mnemonic#"\t$V1, $XBD2, $M3",
4069 imm32zx4_timm:$M3))]> {
4076 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4077 mnemonic#"\t$R1, $M3, $BD2", []> {
4084 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4085 mnemonic#"\t$R1, $M3, $BD2", []> {
4105 imm32zx4:$M3),
4106 mnemonic#"\t$R1, $BDL2, $M3", []> {
4123 (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4124 mnemonic#"\t$V1, $VBD2, $M3", []> {
4133 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4134 mnemonic#"\t$V1, $XBD2, $M3",
4135 [(operator (tr.vt tr.op:$V1), bdxaddr12only:$XBD2, index:$M3)]> {
4219 let M3 = 0;
4250 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4251 mnemonic#"\t$R1, $M3, $BD2", []> {
4258 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4259 mnemonic#"\t$R1, $M3, $BD2", []> {
4330 let M3 = type;
4338 : InstVRRa<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4339 mnemonic#"\t$V1, $V2, $M3", []> {
4347 (ins VR64:$V1, VR64:$V2, imm32zx4:$M3, imm32zx4:$M4),
4348 mnemonic#"\t$V1, $V2, $M3, $M4", []> {
4354 : InstVRRh<opcode, (outs), (ins VR128:$V1, VR128:$V2, imm32zx4:$M3),
4355 mnemonic#"\t$V1, $V2, $M3", []> {
4371 let M3 = 0;
4437 : InstRRFc<opcode, (outs), (ins cls1:$R1, cls2:$R2, imm:$M3),
4438 mnemonic#"\t$R1, $R2, $M3", []>;
4451 (ins cls1:$R1src, cls2:$R2src, imm:$M3),
4452 mnemonic#"\t$R1, $R2, $M3", []> {
4490 (ins imm32zx4:$M3, cls2:$R2, imm32zx4:$M4),
4491 mnemonic#"\t$R1, $M3, $R2, $M4", []>;
4507 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4508 mnemonic#"\t$R1, $M3, $BD2", []> {
4519 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4520 mnemonic#"\t$R1, $M3, $BD2", []> {
4586 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4587 mnemonic#"\t$V1, $I2, $M3",
4589 imm:$I2, index:$M3))]> {
4619 let M3 = type;
4624 (ins VR128:$V2, imm32zx4:$M3, imm32zx4:$M4, imm32zx4:$M5),
4625 mnemonic#"\t$V1, $V2, $M3, $M4, $M5", []>;
4784 imm32zx4:$M3, imm32zx4:$M4),
4785 mnemonic#"\t$R1, $V2, $M3, $M4", []>;
4804 (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4805 mnemonic#"\t$V1, $VBD2, $M3", []> {
4815 (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4816 mnemonic#"\t$V1, $XBD2, $M3",
4819 index:$M3))]> {
5155 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
5195 (ins cls1:$R1src, cls2:$R2, cond4:$valid, cond4:$M3),
5197 cond4:$valid, cond4:$M3))]> {
5226 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
5228 cond4:$valid, cond4:$M3))]> {