Lines Matching refs:I2
212 bits<4> I2;
217 let Inst{3-0} = I2;
241 bits<16> I2;
246 let Inst{15-0} = I2;
283 bits<16> I2;
289 let Inst{31-16} = I2;
320 bits<8> I2;
328 let Inst{15-8} = I2;
339 bits<16> I2;
344 let Inst{31-16} = I2;
393 bits<16> I2;
398 let Inst{31-16} = I2;
409 bits<32> I2;
414 let Inst{31-0} = I2;
451 bits<8> I2;
461 let Inst{15-8} = I2;
895 bits<8> I2;
898 let Inst{23-16} = I2;
910 bits<16> I2;
915 let Inst{15-0} = I2;
925 bits<8> I2;
928 let Inst{39-32} = I2;
1133 bits<16> I2;
1139 let Inst{31-16} = I2;
1152 bits<8> I2;
1159 let Inst{31-24} = I2;
1174 bits<16> I2;
1180 let Inst{31-16} = I2;
1290 bits<16> I2;
1296 let Inst{31-16} = I2;
2257 let I2 = value;
2409 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
2410 mnemonic#"$M3\t$R1, $I2", []>;
2414 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
2415 mnemonic#"\t$R1, $I2, $M3", []>;
2419 : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
2420 mnemonic#V.suffix#"\t$R1, $I2", []> {
2464 (ins cls:$R1, imm:$I2, cond4:$M3, brtarget16:$RI4),
2465 mnemonic#"$M3\t$R1, $I2, $RI4", []>;
2470 (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
2471 mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
2475 : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
2476 mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
2547 (ins cls:$R1, imm:$I2, cond4:$M3, (bdaddr12only $B4, $D4):$BD4),
2548 mnemonic#"$M3\t$R1, $I2, $BD4", []>;
2553 (ins cls:$R1, imm:$I2, imm32zx4:$M3, (bdaddr12only $B4, $D4):$BD4),
2554 mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
2559 (ins cls:$R1, imm:$I2, (bdaddr12only $B4, $D4):$BD4),
2560 mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
2875 : InstSI<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2),
2876 mnemonic#"\t$BD1, $I2",
2877 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2883 : InstSIY<opcode, (outs), (ins (mviaddr20pair $B1, $D1):$BD1, imm:$I2),
2884 mnemonic#"\t$BD1, $I2",
2885 [(operator imm:$I2, mviaddr20pair:$BD1)]> {
2891 : InstSIL<opcode, (outs), (ins (mviaddr12pair $B1, $D1):$BD1, imm:$I2),
2892 mnemonic#"\t$BD1, $I2",
2893 [(operator imm:$I2, mviaddr12pair:$BD1)]> {
2990 let I2 = 0;
3064 : InstRIa<opcode, (outs cls:$R1), (ins imm:$I2),
3065 mnemonic#"\t$R1, $I2",
3066 [(set cls:$R1, (operator imm:$I2))]>;
3070 : InstRILa<opcode, (outs cls:$R1), (ins imm:$I2),
3071 mnemonic#"\t$R1, $I2",
3072 [(set cls:$R1, (operator imm:$I2))]>;
3194 : InstVRIa<opcode, (outs tr.op:$V1), (ins imm:$I2),
3195 mnemonic#"\t$V1, $I2",
3196 [(set (tr.vt tr.op:$V1), (operator (i32 timm:$I2)))]> {
3201 : InstVRIa<opcode, (outs VR128:$V1), (ins imm:$I2, imm32zx4:$M3),
3202 mnemonic#"\t$V1, $I2, $M3", []>;
3334 : InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
3335 mnemonic#"\t$I1, $I2", []>;
3338 : InstSI<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
3339 mnemonic#"\t$BD1, $I2", []>;
3343 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
3344 mnemonic#"\t$BD1, $I2", [(operator bdaddr12only:$BD1, imm:$I2)]>;
3594 : InstRIa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3595 mnemonic#"\t$R1, $I2",
3596 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3603 : InstRIEd<opcode, (outs cls:$R1), (ins cls:$R3, imm:$I2),
3604 mnemonic#"\t$R1, $R3, $I2",
3605 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
3622 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
3623 mnemonic#"$M3\t$R1, $I2",
3624 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
3636 (ins cls:$R1src, imm:$I2, imm32zx4:$M3),
3637 mnemonic#"\t$R1, $I2, $M3", []> {
3645 : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3646 mnemonic#V.suffix#"\t$R1, $I2", []> {
3663 : InstRILa<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
3664 mnemonic#"\t$R1, $I2",
3665 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
3778 : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
3779 mnemonic#"\t$BD1, $I2",
3780 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3787 : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
3788 mnemonic#"\t$BD1, $I2",
3789 [(store (operator (load mode:$BD1), imm:$I2), mode:$BD1)]> {
3814 : InstVRIb<opcode, (outs tr.op:$V1), (ins imm32zx8:$I2, imm32zx8:$I3),
3815 mnemonic#"\t$V1, $I2, $I3",
3816 [(set (tr.vt tr.op:$V1), (operator imm32zx8_timm:$I2, imm32zx8_timm:$I3))]> {
3822 (ins imm32zx8:$I2, imm32zx8:$I3, imm32zx4:$M4),
3823 mnemonic#"\t$V1, $I2, $I3, $M4", []>;
3827 : InstVRIc<opcode, (outs tr1.op:$V1), (ins tr2.op:$V3, imm32zx16:$I2),
3828 mnemonic#"\t$V1, $V3, $I2",
3830 imm32zx16_timm:$I2))]> {
3836 (ins VR128:$V3, imm32zx16:$I2, imm32zx4:$M4),
3837 mnemonic#"\t$V1, $V3, $I2, $M4", []>;
3856 (ins imm32zx16:$I2, imm32zx4:$I3),
3857 mnemonic#"\t$V1, $I2, $I3", []>;
4169 : InstRIa<opcode, (outs), (ins cls:$R1, imm:$I2),
4170 mnemonic#"\t$R1, $I2",
4171 [(set CC, (operator cls:$R1, imm:$I2))]> {
4177 : InstRILa<opcode, (outs), (ins cls:$R1, imm:$I2),
4178 mnemonic#"\t$R1, $I2",
4179 [(set CC, (operator cls:$R1, imm:$I2))]> {
4286 : InstSI<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
4287 mnemonic#"\t$BD1, $I2",
4288 [(set CC, (operator (load mode:$BD1), imm:$I2))]> {
4295 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
4296 mnemonic#"\t$BD1, $I2",
4297 [(set CC, (operator (load bdaddr12only:$BD1), imm:$I2))]> {
4305 : InstSIY<opcode, (outs), (ins (mode $B1, $D1):$BD1, imm:$I2),
4306 mnemonic#"\t$BD1, $I2",
4307 [(set CC, (operator (load mode:$BD1), imm:$I2))]> {
4376 : InstSIL<opcode, (outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
4377 mnemonic#"\t$BD1, $I2",
4378 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
4586 : InstVRIa<opcode, (outs tr1.op:$V1), (ins tr2.op:$V1src, imm:$I2, index:$M3),
4587 mnemonic#"\t$V1, $I2, $M3",
4589 imm:$I2, index:$M3))]> {
5058 : Pseudo<(outs cls:$R1), (ins imm:$I2),
5059 [(set cls:$R1, (operator imm:$I2))]>;
5087 : Pseudo<(outs cls:$R1), (ins cls:$R1src, imm:$I2),
5088 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5095 : Pseudo<(outs cls:$R1), (ins cls:$R3, imm:$I2),
5096 [(set cls:$R1, (operator cls:$R3, imm:$I2))]>;
5168 : Pseudo<(outs), (ins cls:$R1, imm:$I2),
5169 [(set CC, (operator cls:$R1, imm:$I2))]> {
5187 : Pseudo<(outs), (ins (bdaddr12only $B1, $D1):$BD1, imm:$I2),
5188 [(set CC, (operator bdaddr12only:$BD1, imm:$I2))]>;
5226 (ins cls:$R1src, imm:$I2, cond4:$valid, cond4:$M3),
5227 [(set cls:$R1, (z_select_ccmask imm:$I2, cls:$R1src,
5374 : Alias<4, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5375 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5382 : Alias<6, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
5383 [(set cls:$R1, (operator cls:$R1src, imm:$I2))]> {
5394 : Alias<4, (outs), (ins cls:$R1, imm:$I2),
5395 [(set CC, (operator cls:$R1, imm:$I2))]> {