Lines Matching refs:D2
620 bits<12> D2;
626 let Inst{11-0} = D2;
639 bits<12> D2;
645 let Inst{11-0} = D2;
658 bits<12> D2;
665 let Inst{27-16} = D2;
682 bits<12> D2;
688 let Inst{27-16} = D2;
704 bits<20> D2;
710 let Inst{27-16} = D2{11-0};
711 let Inst{15-8} = D2{19-12};
726 bits<20> D2;
732 let Inst{27-16} = D2{11-0};
733 let Inst{15-8} = D2{19-12};
748 bits<12> D2;
754 let Inst{11-0} = D2;
765 bits<12> D2;
771 let Inst{11-0} = D2;
782 bits<12> D2;
788 let Inst{27-16} = D2;
833 bits<12> D2;
840 let Inst{27-16} = D2;
854 bits<20> D2;
860 let Inst{27-16} = D2{11-0};
861 let Inst{15-8} = D2{19-12};
875 bits<20> D2;
881 let Inst{27-16} = D2{11-0};
882 let Inst{15-8} = D2{19-12};
964 bits<12> D2;
971 let Inst{11-0} = D2;
983 bits<12> D2;
992 let Inst{11-0} = D2;
1004 bits<12> D2;
1013 let Inst{11-0} = D2;
1025 bits<12> D2;
1034 let Inst{11-0} = D2;
1044 bits<12> D2;
1053 let Inst{27-16} = D2;
1066 bits<12> D2;
1074 let Inst{11-0} = D2;
1085 bits<12> D2;
1091 let Inst{11-0} = D2;
1102 bits<12> D2;
1111 let Inst{11-0} = D2;
1120 bits<12> D2;
1124 let Inst{11-0} = D2;
1611 bits<12> D2;
1619 let Inst{27-16} = D2;
1634 bits<12> D2;
1642 let Inst{27-16} = D2;
1656 bits<12> D2;
1664 let Inst{27-16} = D2;
1679 bits<12> D2;
1686 let Inst{27-16} = D2;
1701 bits<12> D2;
1708 let Inst{27-16} = D2;
1724 bits<12> D2;
1731 let Inst{27-16} = D2;
1745 bits<12> D2;
1751 let Inst{27-16} = D2;
2263 : InstS<opcode, (outs), (ins (bdaddr12only $B2, $D2):$BD2),
2276 let D2 = 0;
2300 : InstRXa<opcode, (outs), (ins GR64:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2363 (ins cond4:$valid, cond4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2370 (ins imm32zx4:$M1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2374 : InstRXb<opcode, (outs), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
2383 (bdxaddr20only $B2, $D2, $X2):$XBD2),
2391 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2398 : InstRXYb<opcode, (outs), (ins (bdxaddr20only $B2, $D2, $X2):$XBD2),
2576 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, cond4:$M3),
2582 (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2, imm32zx4:$M3),
2594 : InstRSYb<opcode, (outs), (ins cls:$R1, (bdaddr20only $B2, $D2):$BD2),
2631 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2639 (ins cls:$R1src, (bdxaddr20only $B2, $D2, $X2):$XBD2),
2662 (ins cls:$R1src, cls:$R3, (bdaddr12only $B2, $D2):$BD2),
2671 (ins cls:$R1src, cls:$R3, (bdaddr20only $B2, $D2):$BD2),
2679 : InstRSa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2686 : InstRSYa<opcode, (outs cls:$R1, cls:$R3), (ins (mode $B2, $D2):$BD2),
2703 (ins (bdaddr12only $B2, $D2):$BD2, (bdaddr12only $B4, $D4):$BD4),
2711 (ins (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4),
2715 (ins (bdaddr12only $B2, $D2):$BD2),
2735 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2747 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
2771 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2781 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
2789 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2,
2794 (ins VR128:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
2802 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2813 (ins VR128:$V1, GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
2823 (ins VR128:$V1, (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
2832 : InstRSa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2839 : InstRSYa<opcode, (outs), (ins cls:$R1, cls:$R3, (mode $B2, $D2):$BD2),
2857 (bdaddr12only $B2, $D2):$BD2,
2862 (bdaddr12only $B2, $D2):$BD2),
2909 (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2),
2918 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
2930 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2, imm32zx4:$M3),
2940 : InstRSYb<opcode, (outs), (ins cls:$R1, (mode $B2, $D2):$BD2),
2977 : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
2996 : InstS<opcode, (outs), (ins (mode $B2, $D2):$BD2),
3001 : InstRXa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3007 : InstRXYa<opcode, (outs GR64:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3090 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3),
3112 (ins cls:$R1src, (mode $B2, $D2):$BD2, imm32zx4:$M3),
3124 : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2):$BD2),
3147 : InstRXa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3158 : InstRXE<opcode, (outs cls:$R1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3171 : InstRXYa<opcode, (outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
3265 : InstVRX<opcode, (outs tr.op:$V1), (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3275 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3283 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
3287 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2),
3294 : InstRXa<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3299 : InstRXYa<opcode, (outs), (ins cls:$R1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
3348 (bdaddr12only $B2, $D2):$BD2),
3354 (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
3359 (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2),
3364 (ins (bdaddr12only $B1, $D1):$BD1, (bdaddr12only $B2, $D2):$BD2),
3673 (ins cls:$R1src, (shift12only $B2, $D2):$BD2),
3683 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (shift20only $B2, $D2):$BD2),
3700 (ins (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2, imm32zx4:$M3),
3708 : InstRXa<opcode, (outs cls:$R1), (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3722 (ins cls:$R1src, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3739 (ins cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
3752 (ins cls:$R1src, (mode $B2, $D2, $X2):$XBD2),
3807 (ins (bdaddr12pair $B1, $D1):$BD1, (bdaddr12pair $B2, $D2):$BD2),
4016 (ins tr2.op:$V3, (shift12only $B2, $D2):$BD2),
4025 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4:$M4),
4031 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
4042 (ins tr.op:$V3, (shift12only $B2, $D2):$BD2),
4050 (ins VR128:$V3, (shift12only $B2, $D2):$BD2, imm32zx4: $M4),
4056 (ins GR32:$R3, (bdaddr12only $B2, $D2):$BD2),
4066 (ins (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3),
4076 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4084 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4104 (ins cls:$R1, (bdladdr12onlylen8 $B2, $D2, $L2):$BDL2,
4113 (ins (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3),
4123 (ins VR128:$V1, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4133 (ins tr.op:$V1, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4144 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
4199 : InstRXa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4211 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4225 : InstRXYa<opcode, (outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
4250 : InstRSb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4258 : InstRSYb<opcode, (outs), (ins cls:$R1, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4277 (bdladdr12onlylen4 $B2, $D2, $L2):$BDL2),
4363 let D2 = 0;
4368 : InstRXE<opcode, (outs), (ins cls:$R1, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4392 (shift12only $B2, $D2):$BD2, imm32zx4:$I3),
4468 (bdaddr12only $B2, $D2):$BD2, cls:$R3),
4507 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4519 (ins cls:$R1src, imm32zx4:$M3, (mode $B2, $D2):$BD2),
4541 (ins cls1:$R1, cls2:$R3, (bdaddr12only $B2, $D2):$BD2),
4547 (ins cls1:$R1, cls2:$R3, (bdaddr20only $B2, $D2):$BD2),
4553 (ins cls1:$R1src, cls2:$R3src, (shift12only $B2, $D2):$BD2),
4562 (ins cls1:$R1src, cls2:$R3src, (shift20only $B2, $D2):$BD2),
4572 (ins cls2:$R1src, cls2:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2),
4772 (ins tr2.op:$V1src, cls:$R3, (shift12only $B2, $D2):$BD2),
4794 (ins VR128:$V1src, GR64:$R3, (shift12only $B2, $D2):$BD2,
4804 (ins VR128:$V1src, (bdvaddr12only $B2, $D2, $V2):$VBD2, index:$M3),
4815 (ins tr2.op:$V1src, (bdxaddr12only $B2, $D2, $X2):$XBD2, index:$M3),
4944 (ins cls:$R1, (bdaddr12only $B2, $D2):$BD2, cls:$R3,
4950 : InstRSYa<opcode, (outs cls:$R1), (ins cls:$R3, (mode $B2, $D2):$BD2),
4970 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
4982 (ins cls:$R1src, cls:$R3, (mode $B2, $D2):$BD2),
5013 (ins imm32zx4:$M1, (bdxaddr20only $B2, $D2, $X2):$XBD2),
5065 : Pseudo<(outs cls:$R1), (ins (mode $B2, $D2, $X2):$XBD2),
5117 : Pseudo<(outs cls:$R1), (ins cls:$R2, (mode $B2, $D2, $X2):$XBD2), []> {
5140 (ins cls:$R2, cls:$R3, (mode $B2, $D2, $X2):$XBD2), []> {
5155 (ins cls:$R2, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$M3), []> {
5177 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5240 (ins cls:$R1src, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3),
5260 (ins cls:$R1, (mode $B2, $D2):$BD2, cond4:$valid, cond4:$R3), []> {
5269 : Pseudo<(outs), (ins cls:$R1, (mode $B2, $D2, $X2):$XBD2),
5362 : Alias<6, (outs tr.op:$V1), (ins (mode $B2, $D2, $X2):$XBD2),
5368 : Alias<6, (outs), (ins tr.op:$V1, (mode $B2, $D2, $X2):$XBD2),