Lines Matching refs:NegBitShift
4559 SDValue &NegBitShift) { in getCSAddressAndShifts() argument
4575 NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT, in getCSAddressAndShifts()
4607 SDValue AlignedAddr, BitShift, NegBitShift; in lowerATOMIC_LOAD_OP() local
4608 getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift); in lowerATOMIC_LOAD_OP()
4625 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, in lowerATOMIC_LOAD_OP()
4703 SDValue AlignedAddr, BitShift, NegBitShift; in lowerATOMIC_CMP_SWAP() local
4704 getCSAddressAndShifts(Addr, DAG, DL, AlignedAddr, BitShift, NegBitShift); in lowerATOMIC_CMP_SWAP()
4709 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) }; in lowerATOMIC_CMP_SWAP()
8400 Register NegBitShift = MI.getOperand(5).getReg(); in emitAtomicLoadBinary() local
8462 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0); in emitAtomicLoadBinary()
8495 Register NegBitShift = MI.getOperand(5).getReg(); in emitAtomicLoadMinMax() local
8566 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0); in emitAtomicLoadMinMax()
8597 Register NegBitShift = MI.getOperand(6).getReg(); in emitAtomicCmpSwapW() local
8677 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize); in emitAtomicCmpSwapW()