Lines Matching refs:I
64 bool select(MachineInstr &I) override;
78 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
83 MachineInstr &I) const;
85 bool selectGlobalValue(Register ResVReg, MachineInstr &I,
89 MachineInstr &I, Register SrcReg,
91 bool selectUnOp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
95 MachineInstr &I) const;
96 bool selectStore(MachineInstr &I) const;
98 bool selectMemOperation(Register ResVReg, MachineInstr &I) const;
101 MachineInstr &I, unsigned NewOpcode) const;
104 MachineInstr &I) const;
106 bool selectFence(MachineInstr &I) const;
109 MachineInstr &I) const;
112 MachineInstr &I) const;
115 MachineInstr &I) const;
118 unsigned comparisonOpcode, MachineInstr &I) const;
121 MachineInstr &I) const;
123 MachineInstr &I) const;
125 void renderImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
127 void renderFImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
131 MachineInstr &I) const;
133 bool selectSelect(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
135 bool selectIToF(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
137 bool selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I,
141 MachineInstr &I) const;
143 bool selectIntToBool(Register IntReg, Register ResVReg, MachineInstr &I,
147 MachineInstr &I) const;
149 MachineInstr &I) const;
151 MachineInstr &I) const;
153 MachineInstr &I) const;
155 MachineInstr &I) const;
157 MachineInstr &I) const;
159 MachineInstr &I) const;
162 MachineInstr &I) const;
164 bool selectBranch(MachineInstr &I) const;
165 bool selectBranchCond(MachineInstr &I) const;
168 MachineInstr &I) const;
171 MachineInstr &I, CL::OpenCLExtInst CLInst) const;
173 MachineInstr &I, CL::OpenCLExtInst CLInst,
176 MachineInstr &I, const ExtInstList &ExtInsts) const;
179 MachineInstr &I) const;
181 Register buildI32Constant(uint32_t Val, MachineInstr &I,
184 Register buildZerosVal(const SPIRVType *ResType, MachineInstr &I) const;
186 MachineInstr &I) const;
223 bool SPIRVInstructionSelector::select(MachineInstr &I) { in select() argument
224 assert(I.getParent() && "Instruction should be in a basic block!"); in select()
225 assert(I.getParent()->getParent() && "Instruction should be in a function!"); in select()
227 Register Opcode = I.getOpcode(); in select()
231 auto *Def = MRI->getVRegDef(I.getOperand(1).getReg()); in select()
233 auto Res = selectImpl(I, *CoverageInfo); in select()
238 MRI->replaceRegWith(I.getOperand(1).getReg(), I.getOperand(0).getReg()); in select()
239 I.removeFromParent(); in select()
241 } else if (I.getNumDefs() == 1) { in select()
243 MRI->setType(I.getOperand(0).getReg(), LLT::scalar(32)); in select()
245 return constrainSelectedInstRegOperands(I, TII, TRI, RBI); in select()
248 if (I.getNumOperands() != I.getNumExplicitOperands()) { in select()
255 bool HasDefs = I.getNumDefs() > 0; in select()
256 Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0); in select()
258 assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE); in select()
259 if (spvSelect(ResVReg, ResType, I)) { in select()
262 I.removeFromParent(); in select()
270 MachineInstr &I) const { in spvSelect()
271 assert(!isTypeFoldingSupported(I.getOpcode()) || in spvSelect()
272 I.getOpcode() == TargetOpcode::G_CONSTANT); in spvSelect()
273 const unsigned Opcode = I.getOpcode(); in spvSelect()
276 return selectConst(ResVReg, ResType, I.getOperand(1).getCImm()->getValue(), in spvSelect()
277 I); in spvSelect()
279 return selectGlobalValue(ResVReg, I); in spvSelect()
281 return selectOpUndef(ResVReg, ResType, I); in spvSelect()
285 return selectIntrinsic(ResVReg, ResType, I); in spvSelect()
287 return selectBitreverse(ResVReg, ResType, I); in spvSelect()
290 return selectConstVector(ResVReg, ResType, I); in spvSelect()
293 MachineBasicBlock &BB = *I.getParent(); in spvSelect()
294 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorShuffle)) in spvSelect()
297 .addUse(I.getOperand(1).getReg()) in spvSelect()
298 .addUse(I.getOperand(2).getReg()); in spvSelect()
299 for (auto V : I.getOperand(3).getShuffleMask()) in spvSelect()
306 return selectMemOperation(ResVReg, I); in spvSelect()
309 return selectICmp(ResVReg, ResType, I); in spvSelect()
311 return selectFCmp(ResVReg, ResType, I); in spvSelect()
314 return selectFrameIndex(ResVReg, ResType, I); in spvSelect()
317 return selectLoad(ResVReg, ResType, I); in spvSelect()
319 return selectStore(I); in spvSelect()
322 return selectBranch(I); in spvSelect()
324 return selectBranchCond(I); in spvSelect()
327 return selectPhi(ResVReg, ResType, I); in spvSelect()
330 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToS); in spvSelect()
332 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertFToU); in spvSelect()
335 return selectIToF(ResVReg, ResType, I, true, SPIRV::OpConvertSToF); in spvSelect()
337 return selectIToF(ResVReg, ResType, I, false, SPIRV::OpConvertUToF); in spvSelect()
340 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitCount); in spvSelect()
342 return selectExtInst(ResVReg, ResType, I, CL::s_min, GL::SMin); in spvSelect()
344 return selectExtInst(ResVReg, ResType, I, CL::u_min, GL::UMin); in spvSelect()
347 return selectExtInst(ResVReg, ResType, I, CL::s_max, GL::SMax); in spvSelect()
349 return selectExtInst(ResVReg, ResType, I, CL::u_max, GL::UMax); in spvSelect()
352 return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma); in spvSelect()
355 return selectExtInst(ResVReg, ResType, I, CL::pow, GL::Pow); in spvSelect()
357 return selectExtInst(ResVReg, ResType, I, CL::pown); in spvSelect()
360 return selectExtInst(ResVReg, ResType, I, CL::exp, GL::Exp); in spvSelect()
362 return selectExtInst(ResVReg, ResType, I, CL::exp2, GL::Exp2); in spvSelect()
365 return selectExtInst(ResVReg, ResType, I, CL::log, GL::Log); in spvSelect()
367 return selectExtInst(ResVReg, ResType, I, CL::log2, GL::Log2); in spvSelect()
369 return selectLog10(ResVReg, ResType, I); in spvSelect()
372 return selectExtInst(ResVReg, ResType, I, CL::fabs, GL::FAbs); in spvSelect()
374 return selectExtInst(ResVReg, ResType, I, CL::s_abs, GL::SAbs); in spvSelect()
378 return selectExtInst(ResVReg, ResType, I, CL::fmin, GL::FMin); in spvSelect()
381 return selectExtInst(ResVReg, ResType, I, CL::fmax, GL::FMax); in spvSelect()
384 return selectExtInst(ResVReg, ResType, I, CL::copysign); in spvSelect()
387 return selectExtInst(ResVReg, ResType, I, CL::ceil, GL::Ceil); in spvSelect()
389 return selectExtInst(ResVReg, ResType, I, CL::floor, GL::Floor); in spvSelect()
392 return selectExtInst(ResVReg, ResType, I, CL::cos, GL::Cos); in spvSelect()
394 return selectExtInst(ResVReg, ResType, I, CL::sin, GL::Sin); in spvSelect()
397 return selectExtInst(ResVReg, ResType, I, CL::sqrt, GL::Sqrt); in spvSelect()
401 return selectExtInst(ResVReg, ResType, I, CL::ctz); in spvSelect()
404 return selectExtInst(ResVReg, ResType, I, CL::clz); in spvSelect()
407 return selectExtInst(ResVReg, ResType, I, CL::round, GL::Round); in spvSelect()
409 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven); in spvSelect()
411 return selectExtInst(ResVReg, ResType, I, CL::trunc, GL::Trunc); in spvSelect()
414 return selectExtInst(ResVReg, ResType, I, CL::rint, GL::RoundEven); in spvSelect()
417 return selectExtInst(ResVReg, ResType, I, CL::s_mul_hi); in spvSelect()
419 return selectExtInst(ResVReg, ResType, I, CL::u_mul_hi); in spvSelect()
422 return selectExt(ResVReg, ResType, I, true); in spvSelect()
425 return selectExt(ResVReg, ResType, I, false); in spvSelect()
427 return selectTrunc(ResVReg, ResType, I); in spvSelect()
430 return selectUnOp(ResVReg, ResType, I, SPIRV::OpFConvert); in spvSelect()
433 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertPtrToU); in spvSelect()
435 return selectUnOp(ResVReg, ResType, I, SPIRV::OpConvertUToPtr); in spvSelect()
437 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitcast); in spvSelect()
439 return selectAddrSpaceCast(ResVReg, ResType, I); in spvSelect()
445 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg()); in spvSelect()
446 Register GV = I.getOperand(1).getReg(); in spvSelect()
451 isImm(I.getOperand(2), MRI)); in spvSelect()
452 Register Idx = buildZerosVal(GR.getOrCreateSPIRVIntegerType(32, I, TII), I); in spvSelect()
453 MachineBasicBlock &BB = *I.getParent(); in spvSelect()
454 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) in spvSelect()
461 .addUse(I.getOperand(2).getReg()); in spvSelect()
466 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicOr); in spvSelect()
468 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicIAdd); in spvSelect()
470 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicAnd); in spvSelect()
472 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMax); in spvSelect()
474 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicSMin); in spvSelect()
476 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicISub); in spvSelect()
478 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicXor); in spvSelect()
480 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMax); in spvSelect()
482 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicUMin); in spvSelect()
484 return selectAtomicRMW(ResVReg, ResType, I, SPIRV::OpAtomicExchange); in spvSelect()
486 return selectAtomicCmpXchg(ResVReg, ResType, I); in spvSelect()
489 return selectFence(I); in spvSelect()
498 MachineInstr &I, in selectExtInst() argument
500 return selectExtInst(ResVReg, ResType, I, in selectExtInst()
506 MachineInstr &I, in selectExtInst() argument
511 return selectExtInst(ResVReg, ResType, I, ExtInsts); in selectExtInst()
516 MachineInstr &I, in selectExtInst() argument
523 MachineBasicBlock &BB = *I.getParent(); in selectExtInst()
524 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) in selectExtInst()
529 const unsigned NumOps = I.getNumOperands(); in selectExtInst()
531 MIB.add(I.getOperand(i)); in selectExtInst()
540 MachineInstr &I, in selectUnOpWithSrc() argument
543 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) in selectUnOpWithSrc()
552 MachineInstr &I, in selectUnOp() argument
554 return selectUnOpWithSrc(ResVReg, ResType, I, I.getOperand(1).getReg(), in selectUnOp()
599 MachineInstr &I) const { in selectLoad()
600 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0; in selectLoad()
601 Register Ptr = I.getOperand(1 + OpOffset).getReg(); in selectLoad()
602 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpLoad)) in selectLoad()
606 if (!I.getNumMemOperands()) { in selectLoad()
607 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS || in selectLoad()
608 I.getOpcode() == in selectLoad()
610 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB); in selectLoad()
612 addMemoryOperands(*I.memoperands_begin(), MIB); in selectLoad()
617 bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const { in selectStore()
618 unsigned OpOffset = isa<GIntrinsic>(I) ? 1 : 0; in selectStore()
619 Register StoreVal = I.getOperand(0 + OpOffset).getReg(); in selectStore()
620 Register Ptr = I.getOperand(1 + OpOffset).getReg(); in selectStore()
621 MachineBasicBlock &BB = *I.getParent(); in selectStore()
622 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpStore)) in selectStore()
625 if (!I.getNumMemOperands()) { in selectStore()
626 assert(I.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS || in selectStore()
627 I.getOpcode() == in selectStore()
629 addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB); in selectStore()
631 addMemoryOperands(*I.memoperands_begin(), MIB); in selectStore()
637 MachineInstr &I) const { in selectMemOperation()
638 MachineBasicBlock &BB = *I.getParent(); in selectMemOperation()
639 Register SrcReg = I.getOperand(1).getReg(); in selectMemOperation()
640 if (I.getOpcode() == TargetOpcode::G_MEMSET) { in selectMemOperation()
641 assert(I.getOperand(1).isReg() && I.getOperand(2).isReg()); in selectMemOperation()
642 unsigned Val = getIConstVal(I.getOperand(1).getReg(), MRI); in selectMemOperation()
643 unsigned Num = getIConstVal(I.getOperand(2).getReg(), MRI); in selectMemOperation()
644 SPIRVType *ValTy = GR.getOrCreateSPIRVIntegerType(8, I, TII); in selectMemOperation()
645 SPIRVType *ArrTy = GR.getOrCreateSPIRVArrayType(ValTy, Num, I, TII); in selectMemOperation()
646 Register Const = GR.getOrCreateConsIntArray(Val, I, ArrTy, TII); in selectMemOperation()
648 ArrTy, I, TII, SPIRV::StorageClass::UniformConstant); in selectMemOperation()
657 buildOpDecorate(VarReg, I, TII, SPIRV::Decoration::Constant, {}); in selectMemOperation()
658 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVariable)) in selectMemOperation()
665 ValTy, I, TII, SPIRV::StorageClass::UniformConstant); in selectMemOperation()
667 selectUnOpWithSrc(SrcReg, SourceTy, I, VarReg, SPIRV::OpBitcast); in selectMemOperation()
669 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCopyMemorySized)) in selectMemOperation()
670 .addUse(I.getOperand(0).getReg()) in selectMemOperation()
672 .addUse(I.getOperand(2).getReg()); in selectMemOperation()
673 if (I.getNumMemOperands()) in selectMemOperation()
674 addMemoryOperands(*I.memoperands_begin(), MIB); in selectMemOperation()
677 BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY), ResVReg) in selectMemOperation()
684 MachineInstr &I, in selectAtomicRMW() argument
686 assert(I.hasOneMemOperand()); in selectAtomicRMW()
687 const MachineMemOperand *MemOp = *I.memoperands_begin(); in selectAtomicRMW()
689 Register ScopeReg = buildI32Constant(Scope, I); in selectAtomicRMW()
691 Register Ptr = I.getOperand(1).getReg(); in selectAtomicRMW()
697 Register MemSemReg = buildI32Constant(MemSem /*| ScSem*/, I); in selectAtomicRMW()
699 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) in selectAtomicRMW()
705 .addUse(I.getOperand(2).getReg()) in selectAtomicRMW()
709 bool SPIRVInstructionSelector::selectFence(MachineInstr &I) const { in selectFence()
710 AtomicOrdering AO = AtomicOrdering(I.getOperand(0).getImm()); in selectFence()
712 Register MemSemReg = buildI32Constant(MemSem, I); in selectFence()
713 SyncScope::ID Ord = SyncScope::ID(I.getOperand(1).getImm()); in selectFence()
715 Register ScopeReg = buildI32Constant(Scope, I); in selectFence()
716 MachineBasicBlock &BB = *I.getParent(); in selectFence()
717 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpMemoryBarrier)) in selectFence()
725 MachineInstr &I) const { in selectAtomicCmpXchg()
729 Register Ptr = I.getOperand(2).getReg(); in selectAtomicCmpXchg()
730 if (!isa<GIntrinsic>(I)) { in selectAtomicCmpXchg()
731 assert(I.hasOneMemOperand()); in selectAtomicCmpXchg()
732 const MachineMemOperand *MemOp = *I.memoperands_begin(); in selectAtomicCmpXchg()
734 ScopeReg = buildI32Constant(Scope, I); in selectAtomicCmpXchg()
740 MemSemEqReg = buildI32Constant(MemSemEq, I); in selectAtomicCmpXchg()
744 MemSemEq == MemSemNeq ? MemSemEqReg : buildI32Constant(MemSemNeq, I); in selectAtomicCmpXchg()
746 ScopeReg = I.getOperand(5).getReg(); in selectAtomicCmpXchg()
747 MemSemEqReg = I.getOperand(6).getReg(); in selectAtomicCmpXchg()
748 MemSemNeqReg = I.getOperand(7).getReg(); in selectAtomicCmpXchg()
751 Register Cmp = I.getOperand(3).getReg(); in selectAtomicCmpXchg()
752 Register Val = I.getOperand(4).getReg(); in selectAtomicCmpXchg()
755 const DebugLoc &DL = I.getDebugLoc(); in selectAtomicCmpXchg()
757 BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpAtomicCompareExchange)) in selectAtomicCmpXchg()
768 SPIRVType *BoolTy = GR.getOrCreateSPIRVBoolType(I, TII); in selectAtomicCmpXchg()
769 Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpIEqual)) in selectAtomicCmpXchg()
776 Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) in selectAtomicCmpXchg()
780 .addUse(GR.getOrCreateUndef(I, ResType, TII)) in selectAtomicCmpXchg()
783 Result |= BuildMI(*I.getParent(), I, DL, TII.get(SPIRV::OpCompositeInsert)) in selectAtomicCmpXchg()
811 MachineInstr &I) const { in selectAddrSpaceCast()
819 Register NewReg = I.getOperand(1).getReg(); in selectAddrSpaceCast()
820 MachineBasicBlock &BB = *I.getParent(); in selectAddrSpaceCast()
821 SPIRVType *SpvBaseTy = GR.getOrCreateSPIRVIntegerType(8, I, TII); in selectAddrSpaceCast()
822 ResType = GR.getOrCreateSPIRVPointerType(SpvBaseTy, I, TII, in selectAddrSpaceCast()
825 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSpecConstantOp)) in selectAddrSpaceCast()
833 Register SrcPtr = I.getOperand(1).getReg(); in selectAddrSpaceCast()
840 return selectUnOp(ResVReg, ResType, I, SPIRV::OpPtrCastToGeneric); in selectAddrSpaceCast()
843 return selectUnOp(ResVReg, ResType, I, SPIRV::OpGenericCastToPtr); in selectAddrSpaceCast()
848 SrcPtrTy, I, TII, SPIRV::StorageClass::Generic); in selectAddrSpaceCast()
849 MachineBasicBlock &BB = *I.getParent(); in selectAddrSpaceCast()
850 const DebugLoc &DL = I.getDebugLoc(); in selectAddrSpaceCast()
851 bool Success = BuildMI(BB, I, DL, TII.get(SPIRV::OpPtrCastToGeneric)) in selectAddrSpaceCast()
856 return Success && BuildMI(BB, I, DL, TII.get(SPIRV::OpGenericCastToPtr)) in selectAddrSpaceCast()
864 return selectUnOp(ResVReg, ResType, I, SPIRV::OpBitcast); in selectAddrSpaceCast()
957 MachineInstr &I) const { in selectBitreverse()
958 MachineBasicBlock &BB = *I.getParent(); in selectBitreverse()
959 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpBitReverse)) in selectBitreverse()
962 .addUse(I.getOperand(1).getReg()) in selectBitreverse()
968 MachineInstr &I) const { in selectConstVector()
971 I.operands_begin(), I.operands_end(), [this](const MachineOperand &MO) { in selectConstVector()
986 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), in selectConstVector()
990 for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i) in selectConstVector()
991 MIB.addUse(I.getOperand(i).getReg()); in selectConstVector()
998 MachineInstr &I) const { in selectCmp()
999 Register Cmp0 = I.getOperand(2).getReg(); in selectCmp()
1000 Register Cmp1 = I.getOperand(3).getReg(); in selectCmp()
1004 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(CmpOpc)) in selectCmp()
1014 MachineInstr &I) const { in selectICmp()
1015 auto Pred = I.getOperand(1).getPredicate(); in selectICmp()
1018 Register CmpOperand = I.getOperand(2).getReg(); in selectICmp()
1025 return selectCmp(ResVReg, ResType, CmpOpc, I); in selectICmp()
1029 const MachineInstr &I, in renderFImm32() argument
1031 assert(I.getOpcode() == TargetOpcode::G_FCONSTANT && OpIdx == -1 && in renderFImm32()
1033 const ConstantFP *FPImm = I.getOperand(1).getFPImm(); in renderFImm32()
1038 const MachineInstr &I, in renderImm32() argument
1040 assert(I.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && in renderImm32()
1042 addNumImm(I.getOperand(1).getCImm()->getValue(), MIB); in renderImm32()
1046 SPIRVInstructionSelector::buildI32Constant(uint32_t Val, MachineInstr &I, in buildI32Constant() argument
1050 ResType ? ResType : GR.getOrCreateSPIRVIntegerType(32, I, TII); in buildI32Constant()
1058 MachineBasicBlock &BB = *I.getParent(); in buildI32Constant()
1060 MI = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) in buildI32Constant()
1064 MI = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) in buildI32Constant()
1076 MachineInstr &I) const { in selectFCmp()
1077 unsigned CmpOp = getFCmpOpcode(I.getOperand(1).getPredicate()); in selectFCmp()
1078 return selectCmp(ResVReg, ResType, CmpOp, I); in selectFCmp()
1082 MachineInstr &I) const { in buildZerosVal()
1084 return GR.getOrCreateConsIntVector(0, I, ResType, TII); in buildZerosVal()
1085 return GR.getOrCreateConstInt(0, I, ResType, TII); in buildZerosVal()
1090 MachineInstr &I) const { in buildOnesVal()
1095 return GR.getOrCreateConsIntVector(One.getZExtValue(), I, ResType, TII); in buildOnesVal()
1096 return GR.getOrCreateConstInt(One.getZExtValue(), I, ResType, TII); in buildOnesVal()
1101 MachineInstr &I, in selectSelect() argument
1104 Register ZeroReg = buildZerosVal(ResType, I); in selectSelect()
1105 Register OneReg = buildOnesVal(IsSigned, ResType, I); in selectSelect()
1107 GR.isScalarOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool); in selectSelect()
1110 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) in selectSelect()
1113 .addUse(I.getOperand(1).getReg()) in selectSelect()
1121 MachineInstr &I, bool IsSigned, in selectIToF() argument
1123 Register SrcReg = I.getOperand(1).getReg(); in selectIToF()
1126 if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) { in selectIToF()
1128 SPIRVType *TmpType = GR.getOrCreateSPIRVIntegerType(BitWidth, I, TII); in selectIToF()
1131 TmpType = GR.getOrCreateSPIRVVectorType(TmpType, NumElts, I, TII); in selectIToF()
1134 selectSelect(SrcReg, TmpType, I, false); in selectIToF()
1136 return selectUnOpWithSrc(ResVReg, ResType, I, SrcReg, Opcode); in selectIToF()
1141 MachineInstr &I, bool IsSigned) const { in selectExt() argument
1142 if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) in selectExt()
1143 return selectSelect(ResVReg, ResType, I, IsSigned); in selectExt()
1145 return selectUnOp(ResVReg, ResType, I, Opcode); in selectExt()
1150 MachineInstr &I, in selectIntToBool() argument
1157 Register Zero = buildZerosVal(IntTy, I); in selectIntToBool()
1158 Register One = buildOnesVal(false, IntTy, I); in selectIntToBool()
1159 MachineBasicBlock &BB = *I.getParent(); in selectIntToBool()
1160 BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) in selectIntToBool()
1166 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpINotEqual)) in selectIntToBool()
1176 MachineInstr &I) const { in selectTrunc()
1178 Register IntReg = I.getOperand(1).getReg(); in selectTrunc()
1180 return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType); in selectTrunc()
1184 return selectUnOp(ResVReg, ResType, I, Opcode); in selectTrunc()
1190 MachineInstr &I) const { in selectConst()
1193 MachineBasicBlock &BB = *I.getParent(); in selectConst()
1196 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) in selectConst()
1202 Register Reg = GR.getOrCreateConstInt(Imm.getZExtValue(), I, ResType, TII); in selectConst()
1205 return BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY)) in selectConst()
1210 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantI)) in selectConst()
1221 MachineInstr &I) const { in selectOpUndef()
1222 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) in selectOpUndef()
1247 MachineInstr &I) const { in selectInsertVal()
1248 MachineBasicBlock &BB = *I.getParent(); in selectInsertVal()
1249 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeInsert)) in selectInsertVal()
1253 .addUse(I.getOperand(3).getReg()) in selectInsertVal()
1255 .addUse(I.getOperand(2).getReg()); in selectInsertVal()
1256 for (unsigned i = 4; i < I.getNumOperands(); i++) in selectInsertVal()
1257 MIB.addImm(foldImm(I.getOperand(i), MRI)); in selectInsertVal()
1263 MachineInstr &I) const { in selectExtractVal()
1264 MachineBasicBlock &BB = *I.getParent(); in selectExtractVal()
1265 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) in selectExtractVal()
1268 .addUse(I.getOperand(2).getReg()); in selectExtractVal()
1269 for (unsigned i = 3; i < I.getNumOperands(); i++) in selectExtractVal()
1270 MIB.addImm(foldImm(I.getOperand(i), MRI)); in selectExtractVal()
1276 MachineInstr &I) const { in selectInsertElt()
1277 if (isImm(I.getOperand(4), MRI)) in selectInsertElt()
1278 return selectInsertVal(ResVReg, ResType, I); in selectInsertElt()
1279 MachineBasicBlock &BB = *I.getParent(); in selectInsertElt()
1280 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorInsertDynamic)) in selectInsertElt()
1283 .addUse(I.getOperand(2).getReg()) in selectInsertElt()
1284 .addUse(I.getOperand(3).getReg()) in selectInsertElt()
1285 .addUse(I.getOperand(4).getReg()) in selectInsertElt()
1291 MachineInstr &I) const { in selectExtractElt()
1292 if (isImm(I.getOperand(3), MRI)) in selectExtractElt()
1293 return selectExtractVal(ResVReg, ResType, I); in selectExtractElt()
1294 MachineBasicBlock &BB = *I.getParent(); in selectExtractElt()
1295 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpVectorExtractDynamic)) in selectExtractElt()
1298 .addUse(I.getOperand(2).getReg()) in selectExtractElt()
1299 .addUse(I.getOperand(3).getReg()) in selectExtractElt()
1305 MachineInstr &I) const { in selectGEP()
1306 const bool IsGEPInBounds = I.getOperand(2).getImm(); in selectGEP()
1317 auto Res = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode)) in selectGEP()
1321 .addUse(I.getOperand(3).getReg()); in selectGEP()
1327 for (unsigned i = StartingIndex; i < I.getNumExplicitOperands(); ++i) in selectGEP()
1328 Res.addUse(I.getOperand(i).getReg()); in selectGEP()
1334 MachineInstr &I) const { in selectIntrinsic()
1335 MachineBasicBlock &BB = *I.getParent(); in selectIntrinsic()
1336 switch (cast<GIntrinsic>(I).getIntrinsicID()) { in selectIntrinsic()
1338 return selectLoad(ResVReg, ResType, I); in selectIntrinsic()
1340 return selectStore(I); in selectIntrinsic()
1342 return selectExtractVal(ResVReg, ResType, I); in selectIntrinsic()
1344 return selectInsertVal(ResVReg, ResType, I); in selectIntrinsic()
1346 return selectExtractElt(ResVReg, ResType, I); in selectIntrinsic()
1348 return selectInsertElt(ResVReg, ResType, I); in selectIntrinsic()
1350 return selectGEP(ResVReg, ResType, I); in selectIntrinsic()
1353 MachineInstr *MI = MRI->getVRegDef(I.getOperand(1).getReg()); in selectIntrinsic()
1354 MachineInstr *Init = I.getNumExplicitOperands() > 2 in selectIntrinsic()
1355 ? MRI->getVRegDef(I.getOperand(2).getReg()) in selectIntrinsic()
1361 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUndef)) in selectIntrinsic()
1368 bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands(); in selectIntrinsic()
1371 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) in selectIntrinsic()
1376 for (unsigned i = I.getNumExplicitDefs() + 1; in selectIntrinsic()
1377 i < I.getNumExplicitOperands(); ++i) { in selectIntrinsic()
1378 MIB.addUse(I.getOperand(i).getReg()); in selectIntrinsic()
1384 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpName)); in selectIntrinsic()
1385 MIB.addUse(I.getOperand(I.getNumExplicitDefs() + 1).getReg()); in selectIntrinsic()
1386 for (unsigned i = I.getNumExplicitDefs() + 2; in selectIntrinsic()
1387 i < I.getNumExplicitOperands(); ++i) { in selectIntrinsic()
1388 MIB.addImm(I.getOperand(i).getImm()); in selectIntrinsic()
1393 auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpSwitch)); in selectIntrinsic()
1394 for (unsigned i = 1; i < I.getNumExplicitOperands(); ++i) { in selectIntrinsic()
1395 if (I.getOperand(i).isReg()) in selectIntrinsic()
1396 MIB.addReg(I.getOperand(i).getReg()); in selectIntrinsic()
1397 else if (I.getOperand(i).isCImm()) in selectIntrinsic()
1398 addNumImm(I.getOperand(i).getCImm()->getValue(), MIB); in selectIntrinsic()
1399 else if (I.getOperand(i).isMBB()) in selectIntrinsic()
1400 MIB.addMBB(I.getOperand(i).getMBB()); in selectIntrinsic()
1407 return selectAtomicCmpXchg(ResVReg, ResType, I); in selectIntrinsic()
1409 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpUnreachable)); in selectIntrinsic()
1412 return selectFrameIndex(ResVReg, ResType, I); in selectIntrinsic()
1415 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpAssumeTrueKHR)) in selectIntrinsic()
1416 .addUse(I.getOperand(1).getReg()); in selectIntrinsic()
1420 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExpectKHR)) in selectIntrinsic()
1423 .addUse(I.getOperand(2).getReg()) in selectIntrinsic()
1424 .addUse(I.getOperand(3).getReg()); in selectIntrinsic()
1434 MachineInstr &I) const { in selectFrameIndex()
1435 return BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpVariable)) in selectFrameIndex()
1442 bool SPIRVInstructionSelector::selectBranch(MachineInstr &I) const { in selectBranch()
1447 const MachineInstr *PrevI = I.getPrevNode(); in selectBranch()
1448 MachineBasicBlock &MBB = *I.getParent(); in selectBranch()
1450 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) in selectBranch()
1453 .addMBB(I.getOperand(0).getMBB()) in selectBranch()
1456 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranch)) in selectBranch()
1457 .addMBB(I.getOperand(0).getMBB()) in selectBranch()
1461 bool SPIRVInstructionSelector::selectBranchCond(MachineInstr &I) const { in selectBranchCond()
1472 const MachineInstr *NextI = I.getNextNode(); in selectBranchCond()
1478 MachineBasicBlock &MBB = *I.getParent(); in selectBranchCond()
1480 MachineBasicBlock *NextMBB = I.getMF()->getBlockNumbered(NextMBBNum); in selectBranchCond()
1481 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(SPIRV::OpBranchConditional)) in selectBranchCond()
1482 .addUse(I.getOperand(0).getReg()) in selectBranchCond()
1483 .addMBB(I.getOperand(1).getMBB()) in selectBranchCond()
1490 MachineInstr &I) const { in selectPhi()
1491 auto MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpPhi)) in selectPhi()
1494 const unsigned NumOps = I.getNumOperands(); in selectPhi()
1496 MIB.addUse(I.getOperand(i + 0).getReg()); in selectPhi()
1497 MIB.addMBB(I.getOperand(i + 1).getMBB()); in selectPhi()
1503 Register ResVReg, MachineInstr &I, const MachineInstr *Init) const { in selectGlobalValue() argument
1505 MachineIRBuilder MIRBuilder(I); in selectGlobalValue()
1506 const GlobalValue *GV = I.getOperand(1).getGlobal(); in selectGlobalValue()
1514 ArrayElementType, GVType->getArrayNumElements(), I, TII); in selectGlobalValue()
1520 PointerBaseType, I, TII, in selectGlobalValue()
1529 MachineBasicBlock &BB = *I.getParent(); in selectGlobalValue()
1534 return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConstantNull)) in selectGlobalValue()
1540 return BuildMI(BB, I, I.getDebugLoc(), TII.get(TargetOpcode::COPY)) in selectGlobalValue()
1573 MachineInstr &I) const { in selectLog10()
1575 return selectExtInst(ResVReg, ResType, I, CL::log10); in selectLog10()
1583 MachineIRBuilder MIRBuilder(I); in selectLog10()
1584 MachineBasicBlock &BB = *I.getParent(); in selectLog10()
1589 BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst)) in selectLog10()
1594 .add(I.getOperand(1)) in selectLog10()
1612 Result &= BuildMI(BB, I, I.getDebugLoc(), TII.get(Opcode)) in selectLog10()