343 class RISCVPassConfig : public TargetPassConfig {  class
345   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)  in RISCVPassConfig()  function in __anon11c1d7550111::RISCVPassConfig
409   return new RISCVPassConfig(*this, PM);  in createPassConfig()
412 FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {  in createRVVRegAllocPass()
427 bool RISCVPassConfig::addRegAssignAndRewriteFast() {  in addRegAssignAndRewriteFast()
433 bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {  in addRegAssignAndRewriteOptimized()
441 void RISCVPassConfig::addIRPasses() {  in addIRPasses()
456 bool RISCVPassConfig::addPreISel() {  in addPreISel()
473 bool RISCVPassConfig::addInstSelector() {  in addInstSelector()
479 bool RISCVPassConfig::addIRTranslator() {  in addIRTranslator()
484 void RISCVPassConfig::addPreLegalizeMachineIR() {  in addPreLegalizeMachineIR()
492 bool RISCVPassConfig::addLegalizeMachineIR() {  in addLegalizeMachineIR()
497 void RISCVPassConfig::addPreRegBankSelect() {  in addPreRegBankSelect()
502 bool RISCVPassConfig::addRegBankSelect() {  in addRegBankSelect()
507 bool RISCVPassConfig::addGlobalInstructionSelect() {  in addGlobalInstructionSelect()
512 void RISCVPassConfig::addPreSched2() {  in addPreSched2()
519 void RISCVPassConfig::addPreEmitPass() {  in addPreEmitPass()
533 void RISCVPassConfig::addPreEmitPass2() {  in addPreEmitPass2()
553 void RISCVPassConfig::addMachineSSAOptimization() {  in addMachineSSAOptimization()
566 void RISCVPassConfig::addPreRegAlloc() {  in addPreRegAlloc()
578 void RISCVPassConfig::addOptimizedRegAlloc() {  in addOptimizedRegAlloc()
584 void RISCVPassConfig::addFastRegAlloc() {  in addFastRegAlloc()
590 void RISCVPassConfig::addPostRegAlloc() {  in addPostRegAlloc()