Lines Matching refs:NeedGPRC
768 bool NeedGPRC) -> void { in getRegAllocationHints() argument
771 if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(PhysReg))) { in getRegAllocationHints()
780 auto isCompressible = [&Subtarget](const MachineInstr &MI, bool &NeedGPRC) { in getRegAllocationHints() argument
781 NeedGPRC = false; in getRegAllocationHints()
791 NeedGPRC = true; in getRegAllocationHints()
794 NeedGPRC = true; in getRegAllocationHints()
805 NeedGPRC = true; in getRegAllocationHints()
819 NeedGPRC = true; in getRegAllocationHints()
823 NeedGPRC = true; in getRegAllocationHints()
828 NeedGPRC = true; in getRegAllocationHints()
849 bool NeedGPRC; in getRegAllocationHints() local
850 if (isCompressible(MI, NeedGPRC)) { in getRegAllocationHints()
852 if (!NeedGPRC || MI.getNumExplicitOperands() < 3 || in getRegAllocationHints()
855 tryAddHint(MO, MI.getOperand(1), NeedGPRC); in getRegAllocationHints()
857 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1)))) in getRegAllocationHints()
858 tryAddHint(MO, MI.getOperand(2), NeedGPRC); in getRegAllocationHints()
859 } else if (OpIdx == 1 && (!NeedGPRC || MI.getNumExplicitOperands() < 3 || in getRegAllocationHints()
861 tryAddHint(MO, MI.getOperand(0), NeedGPRC); in getRegAllocationHints()
863 (!NeedGPRC || isCompressibleOpnd(MI.getOperand(1)))) { in getRegAllocationHints()
864 tryAddHint(MO, MI.getOperand(0), NeedGPRC); in getRegAllocationHints()