Lines Matching refs:getOpcode
87 if (Hi.getOpcode() != RISCV::LUI && Hi.getOpcode() != RISCV::AUIPC) in INITIALIZE_PASS()
92 Hi.getOpcode() == RISCV::AUIPC ? RISCVII::MO_PCREL_HI : RISCVII::MO_HI; in INITIALIZE_PASS()
105 if (Lo->getOpcode() != RISCV::ADDI) in INITIALIZE_PASS()
109 if (Hi.getOpcode() == RISCV::LUI) { in INITIALIZE_PASS()
115 assert(Hi.getOpcode() == RISCV::AUIPC); in INITIALIZE_PASS()
143 if (Hi.getOpcode() != RISCV::AUIPC) in foldOffset()
178 assert((TailAdd.getOpcode() == RISCV::ADD) && "Expected ADD instruction!"); in foldLargeOffset()
188 if (OffsetTail.getOpcode() == RISCV::ADDI || in foldLargeOffset()
189 OffsetTail.getOpcode() == RISCV::ADDIW) { in foldLargeOffset()
208 if (OffsetLui.getOpcode() != RISCV::LUI || in foldLargeOffset()
215 if (!ST->is64Bit() || OffsetTail.getOpcode() == RISCV::ADDIW) in foldLargeOffset()
226 } else if (OffsetTail.getOpcode() == RISCV::LUI) { in foldLargeOffset()
253 assert((TailShXAdd.getOpcode() == RISCV::SH1ADD || in foldShiftedOffset()
254 TailShXAdd.getOpcode() == RISCV::SH2ADD || in foldShiftedOffset()
255 TailShXAdd.getOpcode() == RISCV::SH3ADD) && in foldShiftedOffset()
269 if (OffsetTail.getOpcode() != RISCV::ADDI) in foldShiftedOffset()
280 switch (TailShXAdd.getOpcode()) { in foldShiftedOffset()
307 switch (Tail.getOpcode()) { in detectAndFoldOffset()
320 if (TailTail.getOpcode() == RISCV::ADDI) { in detectAndFoldOffset()
375 switch (UseMI.getOpcode()) { in foldIntoMemoryOps()
469 if (Hi.getOpcode() != RISCV::AUIPC) in foldIntoMemoryOps()
475 if (UseMI.getOpcode() == RISCV::INLINEASM || in foldIntoMemoryOps()
476 UseMI.getOpcode() == RISCV::INLINEASM_BR) { in foldIntoMemoryOps()