277           uint64_t TSFlags = MBBI->getDesc().TSFlags;  in isConvertibleToVMV_V_V()
360       const MCInstrDesc &Desc = DefMBBI->getDesc();  in copyPhysRegVector()
394       const MCInstrDesc &Desc = DefMBBI->getDesc();  in copyPhysRegVector()
900   assert(LastInst.getDesc().isConditionalBranch() &&  in parseCondBranch()
971     if (J->getDesc().isUnconditionalBranch() ||  in analyzeBranch()
972         J->getDesc().isIndirectBranch()) {  in analyzeBranch()
988   if (I->getDesc().isIndirectBranch())  in analyzeBranch()
1000   if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {  in analyzeBranch()
1006   if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {  in analyzeBranch()
1012   if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&  in analyzeBranch()
1013       I->getDesc().isUnconditionalBranch()) {  in analyzeBranch()
1031   if (!I->getDesc().isUnconditionalBranch() &&  in removeBranch()
1032       !I->getDesc().isConditionalBranch())  in removeBranch()
1045   if (!I->getDesc().isConditionalBranch())  in removeBranch()
1289   assert(MI.getDesc().isBranch() && "Unexpected opcode!");  in getBranchDestBlock()
1470   const MCInstrDesc &DefDesc = DefMI->getDesc();  in optimizeSelect()
1956   MCInstrDesc const &Desc = MI.getDesc();  in verifyInstruction()
2487       MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5))  in getOutliningTypeImpl()
2578   uint64_t TSFlags = MI.getDesc().TSFlags;  in createMIROperandComment()
2590              OpIdx == RISCVII::getSEWOpNum(MI.getDesc())) {  in createMIROperandComment()
2596              OpIdx == RISCVII::getVecPolicyOpNum(MI.getDesc())) {  in createMIROperandComment()
2639   const MCInstrDesc &Desc = MI.getDesc();  in findCommutedOpIndices()
2684     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));  in findCommutedOpIndices()
2704     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags));  in findCommutedOpIndices()
2962     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&  in convertToThreeAddress()
2966     if ((MI.getOperand(RISCVII::getVecPolicyOpNum(MI.getDesc())).getImm() &  in convertToThreeAddress()
2996     assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&  in convertToThreeAddress()