188   bool computeVXRMChanges(const MachineBasicBlock &MBB);
189   void computeAvailable(const MachineBasicBlock &MBB);
190   void computeAnticipated(const MachineBasicBlock &MBB);
191   void emitWriteVXRM(MachineBasicBlock &MBB);
211 bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) {  in computeVXRMChanges()  argument
212   BlockData &BBInfo = BlockInfo[MBB.getNumber()];  in computeVXRMChanges()
215   for (const MachineInstr &MI : MBB) {  in computeVXRMChanges()
239 void RISCVInsertWriteVXRM::computeAvailable(const MachineBasicBlock &MBB) {  in computeAvailable()  argument
240   BlockData &BBInfo = BlockInfo[MBB.getNumber()];  in computeAvailable()
245   if (MBB.pred_empty()) {  in computeAvailable()
248     for (const MachineBasicBlock *P : MBB.predecessors())  in computeAvailable()
258     LLVM_DEBUG(dbgs() << "AvailableIn state of " << printMBBReference(MBB)  in computeAvailable()
269   LLVM_DEBUG(dbgs() << "AvailableOut state of " << printMBBReference(MBB)  in computeAvailable()
273   for (MachineBasicBlock *S : MBB.successors()) {  in computeAvailable()
281 void RISCVInsertWriteVXRM::computeAnticipated(const MachineBasicBlock &MBB) {  in computeAnticipated()  argument
282   BlockData &BBInfo = BlockInfo[MBB.getNumber()];  in computeAnticipated()
287   if (MBB.succ_empty()) {  in computeAnticipated()
290     for (const MachineBasicBlock *S : MBB.successors())  in computeAnticipated()
301     LLVM_DEBUG(dbgs() << "AnticipatedOut state of " << printMBBReference(MBB)  in computeAnticipated()
313   LLVM_DEBUG(dbgs() << "AnticipatedIn state of " << printMBBReference(MBB)  in computeAnticipated()
317   for (MachineBasicBlock *P : MBB.predecessors()) {  in computeAnticipated()
325 void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) {  in emitWriteVXRM()  argument
326   const BlockData &BBInfo = BlockInfo[MBB.getNumber()];  in emitWriteVXRM()
337     if (MBB.isEntryBlock()) {  in emitWriteVXRM()
345       for (MachineBasicBlock *P : MBB.predecessors()) {  in emitWriteVXRM()
367   for (MachineInstr &MI : MBB) {  in emitWriteVXRM()
378         BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))  in emitWriteVXRM()
406     LLVM_DEBUG(dbgs() << "Inserting at end of " << printMBBReference(MBB)  in emitWriteVXRM()
408     BuildMI(MBB, MBB.getFirstTerminator(), DebugLoc(),  in emitWriteVXRM()
427   for (const MachineBasicBlock &MBB : MF)  in runOnMachineFunction()  local
428     NeedVXRMChange |= computeVXRMChanges(MBB);  in runOnMachineFunction()
436   for (const MachineBasicBlock &MBB : MF) {  in runOnMachineFunction()  local
437     WorkList.push(&MBB);  in runOnMachineFunction()
438     BlockInfo[MBB.getNumber()].InQueue = true;  in runOnMachineFunction()
441     const MachineBasicBlock &MBB = *WorkList.front();  in runOnMachineFunction()  local
443     computeAvailable(MBB);  in runOnMachineFunction()
447   for (const MachineBasicBlock &MBB : llvm::reverse(MF)) {  in runOnMachineFunction()  local
448     WorkList.push(&MBB);  in runOnMachineFunction()
449     BlockInfo[MBB.getNumber()].InQueue = true;  in runOnMachineFunction()
452     const MachineBasicBlock &MBB = *WorkList.front();  in runOnMachineFunction()  local
454     computeAnticipated(MBB);  in runOnMachineFunction()
458   for (MachineBasicBlock &MBB : MF)  in runOnMachineFunction()
459     emitWriteVXRM(MBB);  in runOnMachineFunction()