Lines Matching refs:getLMUL1VT
3154 static MVT getLMUL1VT(MVT VT) { in getLMUL1VT() function
3818 assert(M1VT == getLMUL1VT(M1VT)); in lowerBUILD_VECTOR()
4710 assert(M1VT == getLMUL1VT(M1VT)); in lowerShuffleViaVRegSplitting()
7888 SmallerVT = getLMUL1VT(VecVT); in getSmallestVTForIndex()
7890 SmallerVT = getLMUL1VT(VecVT).getDoubleNumVectorElementsVT(); in getSmallestVTForIndex()
7892 SmallerVT = getLMUL1VT(VecVT) in getSmallestVTForIndex()
7949 const MVT M1VT = getLMUL1VT(ContainerVT); in lowerINSERT_VECTOR_ELT()
8162 MVT M1VT = getLMUL1VT(ContainerVT); in lowerEXTRACT_VECTOR_ELT()
8204 MVT LMUL2VT = getLMUL1VT(ContainerVT).getDoubleNumVectorElementsVT(); in lowerEXTRACT_VECTOR_ELT()
9185 const MVT M1VT = getLMUL1VT(VecVT); in lowerReductionSeq()
9477 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerINSERT_SUBVECTOR()
9478 InterSubVT = getLMUL1VT(VecVT); in lowerINSERT_SUBVECTOR()
9627 if (VecVT.bitsGT(getLMUL1VT(VecVT))) { in lowerEXTRACT_SUBVECTOR()
9631 InterSubVT = getLMUL1VT(VecVT); in lowerEXTRACT_SUBVECTOR()
10011 getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) { in lowerFixedLengthVectorLoadToRVV()
10072 getLMUL1VT(ContainerVT).bitsLE(ContainerVT)) in lowerFixedLengthVectorStoreToRVV()
15971 const MVT M1VT = getLMUL1VT(VT); in PerformDAGCombine()
15988 VT.bitsLE(getLMUL1VT(VT)) && Passthru.isUndef()) in PerformDAGCombine()
15996 const MVT M1VT = getLMUL1VT(VecVT); in PerformDAGCombine()