Lines Matching refs:addRegisterClass

120   addRegisterClass(XLenVT, &RISCV::GPRRegClass);  in RISCVTargetLowering()
122     addRegisterClass(MVT::i32, &RISCV::GPRRegClass);  in RISCVTargetLowering()
125     addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);  in RISCVTargetLowering()
127     addRegisterClass(MVT::bf16, &RISCV::FPR16RegClass);  in RISCVTargetLowering()
129     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);  in RISCVTargetLowering()
131     addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);  in RISCVTargetLowering()
133     addRegisterClass(MVT::f16, &RISCV::GPRF16RegClass);  in RISCVTargetLowering()
135     addRegisterClass(MVT::f32, &RISCV::GPRF32RegClass);  in RISCVTargetLowering()
138       addRegisterClass(MVT::f64, &RISCV::GPRRegClass);  in RISCVTargetLowering()
140       addRegisterClass(MVT::f64, &RISCV::GPRPairRegClass);  in RISCVTargetLowering()
184       addRegisterClass(VT, RC);  in RISCVTargetLowering()
217         addRegisterClass(VT, TRI.getRegClass(RCID));  in RISCVTargetLowering()