Lines Matching refs:M1VT
3817 MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget); in lowerBUILD_VECTOR() local
3818 assert(M1VT == getLMUL1VT(M1VT)); in lowerBUILD_VECTOR()
3825 unsigned NumOpElts = M1VT.getVectorMinNumElements(); in lowerBUILD_VECTOR()
3831 SubBV = convertToScalableVector(M1VT, SubBV, DAG, Subtarget); in lowerBUILD_VECTOR()
4709 MVT M1VT = getContainerForFixedLengthVector(DAG, OneRegVT, Subtarget); in lowerShuffleViaVRegSplitting() local
4710 assert(M1VT == getLMUL1VT(M1VT)); in lowerShuffleViaVRegSplitting()
4711 unsigned NumOpElts = M1VT.getVectorMinNumElements(); in lowerShuffleViaVRegSplitting()
4724 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, SrcVec, in lowerShuffleViaVRegSplitting()
4728 SubVec = convertToScalableVector(M1VT, SubVec, DAG, Subtarget); in lowerShuffleViaVRegSplitting()
7949 const MVT M1VT = getLMUL1VT(ContainerVT); in lowerINSERT_VECTOR_ELT() local
7950 if (MinVLen == MaxVLen && ContainerVT.bitsGT(M1VT)) { in lowerINSERT_VECTOR_ELT()
7956 SubRegIdx * M1VT.getVectorElementCount().getKnownMinValue(); in lowerINSERT_VECTOR_ELT()
7959 ContainerVT = M1VT; in lowerINSERT_VECTOR_ELT()
8162 MVT M1VT = getLMUL1VT(ContainerVT); in lowerEXTRACT_VECTOR_ELT() local
8169 SubRegIdx * M1VT.getVectorElementCount().getKnownMinValue(); in lowerEXTRACT_VECTOR_ELT()
8170 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Vec, in lowerEXTRACT_VECTOR_ELT()
8173 ContainerVT = M1VT; in lowerEXTRACT_VECTOR_ELT()
9185 const MVT M1VT = getLMUL1VT(VecVT); in lowerReductionSeq() local
9191 auto InnerVT = VecVT.bitsLE(M1VT) ? VecVT : M1VT; in lowerReductionSeq()
9198 if (M1VT != InnerVT) in lowerReductionSeq()
9199 InitialValue = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, M1VT, in lowerReductionSeq()
9200 DAG.getUNDEF(M1VT), in lowerReductionSeq()
9202 SDValue PassThru = NonZeroAVL ? DAG.getUNDEF(M1VT) : InitialValue; in lowerReductionSeq()
9205 SDValue Reduction = DAG.getNode(RVVOpcode, DL, M1VT, Ops); in lowerReductionSeq()
15971 const MVT M1VT = getLMUL1VT(VT); in PerformDAGCombine() local
15972 if (M1VT.bitsLT(VT)) { in PerformDAGCombine()
15974 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Passthru, in PerformDAGCombine()
15977 DAG.getNode(N->getOpcode(), DL, M1VT, M1Passthru, Scalar, VL); in PerformDAGCombine()
15996 const MVT M1VT = getLMUL1VT(VecVT); in PerformDAGCombine() local
15997 if (M1VT.bitsLT(VecVT)) { in PerformDAGCombine()
15998 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Vec, in PerformDAGCombine()