11682     bool IsAdd = N->getOpcode() == ISD::UADDO;  in ReplaceNodeResults()  local
11687         DAG.getNode(IsAdd ? ISD::ADD : ISD::SUB, DL, MVT::i64, LHS, RHS);  in ReplaceNodeResults()
11692     if (IsAdd && isOneConstant(RHS)) {  in ReplaceNodeResults()
11700     } else if (IsAdd && isAllOnesConstant(RHS)) {  in ReplaceNodeResults()
11710                               IsAdd ? ISD::SETULT : ISD::SETUGT);  in ReplaceNodeResults()
14220   bool IsAdd = N->getOpcode() == RISCVISD::FADD_VL;  in performFADDSUB_VLCombine()  local
14239     if (!IsAdd)  in performFADDSUB_VLCombine()
14256   if (IsAdd)  in performFADDSUB_VLCombine()
14310   bool IsAdd = N0.getOpcode() == ISD::ADD;  in performSRACombine()  local
14311   if ((IsAdd || N0.getOpcode() == ISD::SUB)) {  in performSRACombine()
14313     AddC = dyn_cast<ConstantSDNode>(N0.getOperand(IsAdd ? 1 : 0));  in performSRACombine()
14331     Shl = N0.getOperand(IsAdd ? 0 : 1);  in performSRACombine()
14357     if (IsAdd)  in performSRACombine()