50 void RISCVDAGToDAGISel::PreprocessISelDAG() {  in PreprocessISelDAG()
141 void RISCVDAGToDAGISel::PostprocessISelDAG() {  in PostprocessISelDAG()
294 void RISCVDAGToDAGISel::addVectorLoadStoreOperands(  in addVectorLoadStoreOperands()
340 void RISCVDAGToDAGISel::selectVLSEG(SDNode *Node, bool IsMasked,  in selectVLSEG()
380 void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node, bool IsMasked) {  in selectVLSEGFF()
422 void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked,  in selectVLXSEG()
473 void RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, bool IsMasked,  in selectVSSEG()
505 void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,  in selectVSXSEG()
547 void RISCVDAGToDAGISel::selectVSETVLI(SDNode *Node) {  in selectVSETVLI()
606 bool RISCVDAGToDAGISel::tryShrinkShlLogicImm(SDNode *Node) {  in tryShrinkShlLogicImm()
684 bool RISCVDAGToDAGISel::trySignedBitfieldExtract(SDNode *Node) {  in trySignedBitfieldExtract()
751 bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {  in tryIndexedLoad()
820 void RISCVDAGToDAGISel::Select(SDNode *Node) {  in Select()
2194 bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(  in SelectInlineAsmMemoryOperand()
2223 bool RISCVDAGToDAGISel::SelectAddrFrameIndex(SDValue Addr, SDValue &Base,  in SelectAddrFrameIndex()
2235 bool RISCVDAGToDAGISel::SelectFrameAddrRegImm(SDValue Addr, SDValue &Base,  in SelectFrameAddrRegImm()
2333 bool RISCVDAGToDAGISel::SelectAddrRegRegScale(SDValue Addr,  in SelectAddrRegRegScale()
2387 bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,  in SelectAddrRegImm()
2481 bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,  in SelectAddrRegImmLsb00000()
2545 bool RISCVDAGToDAGISel::selectShiftMask(SDValue N, unsigned ShiftWidth,  in selectShiftMask()
2622 bool RISCVDAGToDAGISel::selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,  in selectSETCC()
2681 bool RISCVDAGToDAGISel::selectSExtBits(SDValue N, unsigned Bits, SDValue &Val) {  in selectSExtBits()
2710 bool RISCVDAGToDAGISel::selectZExtBits(SDValue N, unsigned Bits, SDValue &Val) {  in selectZExtBits()
2731 bool RISCVDAGToDAGISel::selectSHXADDOp(SDValue N, unsigned ShAmt,  in selectSHXADDOp()
2826 bool RISCVDAGToDAGISel::selectSHXADD_UWOp(SDValue N, unsigned ShAmt,  in selectSHXADD_UWOp()
2899 bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,  in hasAllNBitUsers()
3057 bool RISCVDAGToDAGISel::selectSimm5Shl2(SDValue N, SDValue &Simm5,  in selectSimm5Shl2()
3081 bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {  in selectVLOp()
3120 bool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {  in selectVSplat()
3159 bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {  in selectVSplatSimm5()
3164 bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {  in selectVSplatSimm5Plus1()
3170 bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1NonZero(SDValue N,  in selectVSplatSimm5Plus1NonZero()
3178 bool RISCVDAGToDAGISel::selectVSplatUimm(SDValue N, unsigned Bits,  in selectVSplatUimm()
3185 bool RISCVDAGToDAGISel::selectLow8BitsVSplat(SDValue N, SDValue &SplatVal) {  in selectLow8BitsVSplat()
3211 bool RISCVDAGToDAGISel::selectFPImm(SDValue N, SDValue &Imm) {  in selectFPImm()
3241 bool RISCVDAGToDAGISel::selectRVVSimm5(SDValue N, unsigned Width,  in selectRVVSimm5()
3258 bool RISCVDAGToDAGISel::doPeepholeSExtW(SDNode *N) {  in doPeepholeSExtW()
3380 bool RISCVDAGToDAGISel::doPeepholeMaskedRVV(MachineSDNode *N) {  in doPeepholeMaskedRVV()
3474 bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {  in performCombineVMergeAndVOps()
3717 bool RISCVDAGToDAGISel::doPeepholeMergeVVMFold() {  in doPeepholeMergeVVMFold()
3737 bool RISCVDAGToDAGISel::doPeepholeNoRegPassThru() {  in doPeepholeNoRegPassThru()
3774   return new RISCVDAGToDAGISel(TM, OptLevel);  in createRISCVISelDag()
3777 char RISCVDAGToDAGISel::ID = 0;
3779 INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)