Lines Matching refs:OutMI
107 bool lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
878 MCInst &OutMI) { in lowerRISCVVMachineInstrToMCInst() argument
884 OutMI.setOpcode(RVV->BaseInstr); in lowerRISCVVMachineInstrToMCInst()
922 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode()); in lowerRISCVVMachineInstrToMCInst()
925 if (OutMCID.getOperandConstraint(OutMI.getNumOperands(), MCOI::TIED_TO) < in lowerRISCVVMachineInstrToMCInst()
972 OutMI.addOperand(MCOp); in lowerRISCVVMachineInstrToMCInst()
977 const MCInstrDesc &OutMCID = TII->get(OutMI.getOpcode()); in lowerRISCVVMachineInstrToMCInst()
978 if (OutMI.getNumOperands() < OutMCID.getNumOperands()) { in lowerRISCVVMachineInstrToMCInst()
979 assert(OutMCID.operands()[OutMI.getNumOperands()].RegClass == in lowerRISCVVMachineInstrToMCInst()
982 OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister)); in lowerRISCVVMachineInstrToMCInst()
985 assert(OutMI.getNumOperands() == OutMCID.getNumOperands()); in lowerRISCVVMachineInstrToMCInst()
989 bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) { in lowerToMCInst() argument
990 if (lowerRISCVVMachineInstrToMCInst(MI, OutMI)) in lowerToMCInst()
993 OutMI.setOpcode(MI->getOpcode()); in lowerToMCInst()
998 OutMI.addOperand(MCOp); in lowerToMCInst()
1001 switch (OutMI.getOpcode()) { in lowerToMCInst()