Lines Matching refs:isUInt
629 (isRV64Imm() || (isInt<32>(Imm) || isUInt<32>(Imm))); in isImmXLenLI()
643 (isRV64Imm() || (isInt<32>(Imm) || isUInt<32>(Imm))); in isImmXLenLI_Restricted()
654 return (isRV64Imm() && isUInt<6>(Imm)) || isUInt<5>(Imm); in isUImmLog2XLen()
667 return (isRV64Imm() && isUInt<6>(Imm)) || isUInt<5>(Imm); in isUImmLog2XLenNonZero()
678 return (isRV64Imm() && isUInt<5>(Imm)) || isUInt<4>(Imm); in isUImmLog2XLenHalf()
687 return IsConstantImm && isUInt<N>(Imm) && VK == RISCVMCExpr::VK_RISCV_None; in IsUImm()
706 return IsConstantImm && isUInt<8>(Imm) && Imm >= 32 && in isUImm8GE32()
788 (isUInt<5>(Imm) || (Imm >= 0xfffe0 && Imm <= 0xfffff)) && in isCLUIImm()
857 if (IsRV64Imm || !isUInt<32>(Imm)) in fixImmediateForRV32()
917 return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || in isUImm20LUI()
939 return isUInt<20>(Imm) && (VK == RISCVMCExpr::VK_RISCV_None || in isUImm20AUIPC()
1740 if (isUInt<7>(Imm)) { in parseInsnDirectiveOpcode()
1755 assert(isUInt<7>(Opcode->Value) && (Opcode->Value & 0x3) == 3 && in parseInsnDirectiveOpcode()
1854 if (isUInt<12>(Imm)) { in parseCSRSystemRegister()