Lines Matching refs:PPC
140 BuildMI(MBB, At, At->getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), Reg); in addDummyDef()
166 assert((MF.getRegInfo().use_empty(PPC::X2) || in runOnMachineFunction()
226 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in getKnownLeadingZeroCount()
227 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec) in getKnownLeadingZeroCount()
230 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in getKnownLeadingZeroCount()
234 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in getKnownLeadingZeroCount()
235 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in getKnownLeadingZeroCount()
236 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in getKnownLeadingZeroCount()
240 if (Opcode == PPC::ANDI_rec) { in getKnownLeadingZeroCount()
245 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZW_rec || in getKnownLeadingZeroCount()
246 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZW_rec || in getKnownLeadingZeroCount()
247 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8) in getKnownLeadingZeroCount()
251 if (Opcode == PPC::CNTLZD || Opcode == PPC::CNTLZD_rec || in getKnownLeadingZeroCount()
252 Opcode == PPC::CNTTZD || Opcode == PPC::CNTTZD_rec) in getKnownLeadingZeroCount()
256 if (Opcode == PPC::LHZ || Opcode == PPC::LHZX || in getKnownLeadingZeroCount()
257 Opcode == PPC::LHZ8 || Opcode == PPC::LHZX8 || in getKnownLeadingZeroCount()
258 Opcode == PPC::LHZU || Opcode == PPC::LHZUX || in getKnownLeadingZeroCount()
259 Opcode == PPC::LHZU8 || Opcode == PPC::LHZUX8) in getKnownLeadingZeroCount()
262 if (Opcode == PPC::LBZ || Opcode == PPC::LBZX || in getKnownLeadingZeroCount()
263 Opcode == PPC::LBZ8 || Opcode == PPC::LBZX8 || in getKnownLeadingZeroCount()
264 Opcode == PPC::LBZU || Opcode == PPC::LBZUX || in getKnownLeadingZeroCount()
265 Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8) in getKnownLeadingZeroCount()
268 if (Opcode == PPC::AND || Opcode == PPC::AND8 || Opcode == PPC::AND_rec || in getKnownLeadingZeroCount()
269 Opcode == PPC::AND8_rec) in getKnownLeadingZeroCount()
274 if (Opcode == PPC::OR || Opcode == PPC::OR8 || Opcode == PPC::XOR || in getKnownLeadingZeroCount()
275 Opcode == PPC::XOR8 || Opcode == PPC::OR_rec || in getKnownLeadingZeroCount()
276 Opcode == PPC::OR8_rec || Opcode == PPC::XOR_rec || in getKnownLeadingZeroCount()
277 Opcode == PPC::XOR8_rec) in getKnownLeadingZeroCount()
362 if (Opcode == PPC::COPY) { in collectUnprimedAccPHIs()
364 if (!Reg.isVirtual() || MRI->getRegClass(Reg) != &PPC::ACCRCRegClass) in collectUnprimedAccPHIs()
366 } else if (Opcode != PPC::IMPLICIT_DEF && Opcode != PPC::PHI) in collectUnprimedAccPHIs()
372 if (Opcode != PPC::PHI) in collectUnprimedAccPHIs()
402 assert((Opcode == PPC::COPY || Opcode == PPC::IMPLICIT_DEF || in convertUnprimedAccPHIs()
403 Opcode == PPC::PHI) && in convertUnprimedAccPHIs()
405 if (Opcode == PPC::COPY) { in convertUnprimedAccPHIs()
407 &PPC::ACCRCRegClass && in convertUnprimedAccPHIs()
410 } else if (Opcode == PPC::IMPLICIT_DEF) { in convertUnprimedAccPHIs()
411 Register AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass); in convertUnprimedAccPHIs()
413 TII->get(PPC::IMPLICIT_DEF), AccReg); in convertUnprimedAccPHIs()
416 } else if (Opcode == PPC::PHI) { in convertUnprimedAccPHIs()
435 AccReg = MRI->createVirtualRegister(&PPC::ACCRCRegClass); in convertUnprimedAccPHIs()
437 *PHI->getParent(), PHI, PHI->getDebugLoc(), TII->get(PPC::PHI), AccReg); in convertUnprimedAccPHIs()
512 MO.setReg(PPC::NoRegister); in simplifyCode()
546 case PPC::COPY: { in simplifyCode()
551 if (MRI->getRegClass(Src) != &PPC::UACCRCRegClass || in simplifyCode()
552 MRI->getRegClass(Dst) != &PPC::ACCRCRegClass) in simplifyCode()
565 if (RootPHI->getOpcode() != PPC::PHI) in simplifyCode()
577 case PPC::LI: in simplifyCode()
578 case PPC::LI8: { in simplifyCode()
597 case PPC::STW: in simplifyCode()
598 case PPC::STD: { in simplifyCode()
611 case PPC::XXPERMDI: { in simplifyCode()
646 if (DefOpc != PPC::XVCVDPSXDS && DefOpc != PPC::XVCVDPUXDS) in simplifyCode()
652 if (LoadMI && LoadMI->getOpcode() == PPC::LXVDSX) in simplifyCode()
658 (DefOpc == PPC::LXVDSX || isConversionOfLoadAndSplat())) { in simplifyCode()
662 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
672 if (DefOpc == PPC::XXPERMDI) { in simplifyCode()
692 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
722 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
731 DefOpc == PPC::XXPERMDIs && in simplifyCode()
740 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
752 (DefOpc == PPC::VSPLTB || DefOpc == PPC::VSPLTH || in simplifyCode()
753 DefOpc == PPC::VSPLTW || DefOpc == PPC::XXSPLTW || in simplifyCode()
754 DefOpc == PPC::VSPLTISB || DefOpc == PPC::VSPLTISH || in simplifyCode()
755 DefOpc == PPC::VSPLTISW)) { in simplifyCode()
762 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
776 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
784 case PPC::VSPLTB: in simplifyCode()
785 case PPC::VSPLTH: in simplifyCode()
786 case PPC::XXSPLTW: { in simplifyCode()
788 unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2; in simplifyCode()
798 if (DefOpcode != PPC::XVCVSPSXWS && DefOpcode != PPC::XVCVSPUXWS) in simplifyCode()
804 return Splt && (Splt->getOpcode() == PPC::LXVWSX || in simplifyCode()
805 Splt->getOpcode() == PPC::XXSPLTW); in simplifyCode()
808 (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) || in simplifyCode()
809 (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) || in simplifyCode()
810 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs) || in simplifyCode()
811 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::LXVWSX) || in simplifyCode()
812 (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::MTVSRWS)|| in simplifyCode()
813 (MyOpcode == PPC::XXSPLTW && isConvertOfSplat()); in simplifyCode()
819 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
828 if (DefOpcode == PPC::XXSLDWI) { in simplifyCode()
834 MI.getOperand(MyOpcode == PPC::XXSPLTW ? 2 : 1).getImm(); in simplifyCode()
854 case PPC::XVCVDPSP: { in simplifyCode()
864 if (DefMI && DefMI->getOpcode() == PPC::XXPERMDI) { in simplifyCode()
882 if ((Opc == PPC::FRSP || Opc == PPC::XSRSP) && in simplifyCode()
916 case PPC::EXTSH: in simplifyCode()
917 case PPC::EXTSH8: in simplifyCode()
918 case PPC::EXTSH8_32_64: { in simplifyCode()
928 if (SrcOpcode == PPC::LHZ || SrcOpcode == PPC::LHZX) { in simplifyCode()
935 unsigned Opc = PPC::LHA; in simplifyCode()
936 bool SourceIsXForm = SrcOpcode == PPC::LHZX; in simplifyCode()
937 bool MIIs64Bit = MI.getOpcode() == PPC::EXTSH8 || in simplifyCode()
938 MI.getOpcode() == PPC::EXTSH8_32_64; in simplifyCode()
941 Opc = PPC::LHAX8; in simplifyCode()
943 Opc = PPC::LHAX; in simplifyCode()
945 Opc = PPC::LHA8; in simplifyCode()
967 case PPC::EXTSW: in simplifyCode()
968 case PPC::EXTSW_32: in simplifyCode()
969 case PPC::EXTSW_32_64: { in simplifyCode()
979 if (SrcOpcode == PPC::LWZ || SrcOpcode == PPC::LWZX) { in simplifyCode()
1004 unsigned Opc = PPC::LWA_32; in simplifyCode()
1005 bool SourceIsXForm = SrcOpcode == PPC::LWZX; in simplifyCode()
1006 bool MIIs64Bit = MI.getOpcode() == PPC::EXTSW || in simplifyCode()
1007 MI.getOpcode() == PPC::EXTSW_32_64; in simplifyCode()
1010 Opc = PPC::LWAX; in simplifyCode()
1012 Opc = PPC::LWAX_32; in simplifyCode()
1014 Opc = PPC::LWA; in simplifyCode()
1016 if (!IsWordAligned && (Opc == PPC::LWA || Opc == PPC::LWA_32)) in simplifyCode()
1036 } else if (MI.getOpcode() == PPC::EXTSW_32_64 && in simplifyCode()
1042 MF->getRegInfo().createVirtualRegister(&PPC::G8RCRegClass); in simplifyCode()
1043 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::IMPLICIT_DEF), in simplifyCode()
1045 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::INSERT_SUBREG), in simplifyCode()
1049 .addImm(PPC::sub_32); in simplifyCode()
1056 case PPC::RLDICL: { in simplifyCode()
1073 if (!(SrcMI && SrcMI->getOpcode() == PPC::INSERT_SUBREG && in simplifyCode()
1080 if (ImpDefMI->getOpcode() != PPC::IMPLICIT_DEF) break; in simplifyCode()
1083 if (SubRegMI->getOpcode() == PPC::COPY) { in simplifyCode()
1095 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
1110 case PPC::ADD4: in simplifyCode()
1111 case PPC::ADD8: { in simplifyCode()
1116 return DefPhiMI && (DefPhiMI->getOpcode() == PPC::PHI) && in simplifyCode()
1133 (LiMI->getOpcode() != PPC::LI && LiMI->getOpcode() != PPC::LI8) in simplifyCode()
1152 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode()
1153 ? &PPC::G8RC_and_G8RC_NOX0RegClass in simplifyCode()
1154 : &PPC::GPRC_and_GPRC_NOR0RegClass; in simplifyCode()
1167 if (LiMI->getOpcode() == PPC::ADDI || LiMI->getOpcode() == PPC::ADDI8) in simplifyCode()
1170 assert((LiMI->getOpcode() == PPC::LI || in simplifyCode()
1171 LiMI->getOpcode() == PPC::LI8) && in simplifyCode()
1175 LiMI->setDesc(TII->get(LiMI->getOpcode() == PPC::LI ? PPC::ADDI in simplifyCode()
1176 : PPC::ADDI8)); in simplifyCode()
1186 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY), in simplifyCode()
1196 case PPC::RLDICR: { in simplifyCode()
1201 case PPC::ANDI_rec: in simplifyCode()
1202 case PPC::ANDI8_rec: in simplifyCode()
1203 case PPC::ANDIS_rec: in simplifyCode()
1204 case PPC::ANDIS8_rec: { in simplifyCode()
1215 if (SrcOpCode != PPC::RLDICL && SrcOpCode != PPC::RLDICR) in simplifyCode()
1227 if (MI.getOpcode() == PPC::ANDIS_rec || in simplifyCode()
1228 MI.getOpcode() == PPC::ANDIS8_rec) in simplifyCode()
1237 (SrcOpCode == PPC::RLDICL && (RZeroAndImm + ImmSrc > 63)) || in simplifyCode()
1238 (SrcOpCode == PPC::RLDICR && LZeroAndImm > ImmSrc); in simplifyCode()
1244 ((SrcOpCode == PPC::RLDICL && LZeroAndImm >= ImmSrc) || in simplifyCode()
1245 (SrcOpCode == PPC::RLDICR && (RZeroAndImm + ImmSrc > 63))); in simplifyCode()
1263 case PPC::RLWINM: in simplifyCode()
1264 case PPC::RLWINM_rec: in simplifyCode()
1265 case PPC::RLWINM8: in simplifyCode()
1266 case PPC::RLWINM8_rec: { in simplifyCode()
1271 : PPC::NoRegister; in simplifyCode()
1283 case PPC::TDI: in simplifyCode()
1284 case PPC::TWI: in simplifyCode()
1285 case PPC::TD: in simplifyCode()
1286 case PPC::TW: { in simplifyCode()
1293 if (!(LiMI1 && (LiMI1->getOpcode() == PPC::LI || in simplifyCode()
1294 LiMI1->getOpcode() == PPC::LI8))) in simplifyCode()
1297 !(LiMI2 && (LiMI2->getOpcode() == PPC::LI || in simplifyCode()
1298 LiMI2->getOpcode() == PPC::LI8))) in simplifyCode()
1318 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::TRAP)); in simplifyCode()
1362 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); in isEqOrNe()
1363 unsigned PredCond = PPC::getPredicateCondition(Pred); in isEqOrNe()
1364 return (PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE); in isEqOrNe()
1368 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || in isSupportedCmpOp()
1369 opCode == PPC::CMPLW || opCode == PPC::CMPW || in isSupportedCmpOp()
1370 opCode == PPC::CMPLDI || opCode == PPC::CMPDI || in isSupportedCmpOp()
1371 opCode == PPC::CMPLWI || opCode == PPC::CMPWI); in isSupportedCmpOp()
1375 return (opCode == PPC::CMPLD || opCode == PPC::CMPD || in is64bitCmpOp()
1376 opCode == PPC::CMPLDI || opCode == PPC::CMPDI); in is64bitCmpOp()
1380 return (opCode == PPC::CMPD || opCode == PPC::CMPW || in isSignedCmpOp()
1381 opCode == PPC::CMPDI || opCode == PPC::CMPWI); in isSignedCmpOp()
1385 if (opCode == PPC::CMPLD) return PPC::CMPD; in getSignedCmpOpCode()
1386 if (opCode == PPC::CMPLW) return PPC::CMPW; in getSignedCmpOpCode()
1387 if (opCode == PPC::CMPLDI) return PPC::CMPDI; in getSignedCmpOpCode()
1388 if (opCode == PPC::CMPLWI) return PPC::CMPWI; in getSignedCmpOpCode()
1400 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); in getPredicateToDecImm()
1401 unsigned PredCond = PPC::getPredicateCondition(Pred); in getPredicateToDecImm()
1402 unsigned PredHint = PPC::getPredicateHint(Pred); in getPredicateToDecImm()
1403 if (PredCond == PPC::PRED_GE) in getPredicateToDecImm()
1404 return PPC::getPredicate(PPC::PRED_GT, PredHint); in getPredicateToDecImm()
1405 if (PredCond == PPC::PRED_LT) in getPredicateToDecImm()
1406 return PPC::getPredicate(PPC::PRED_LE, PredHint); in getPredicateToDecImm()
1419 PPC::Predicate Pred = (PPC::Predicate)BI->getOperand(0).getImm(); in getPredicateToIncImm()
1420 unsigned PredCond = PPC::getPredicateCondition(Pred); in getPredicateToIncImm()
1421 unsigned PredHint = PPC::getPredicateHint(Pred); in getPredicateToIncImm()
1422 if (PredCond == PPC::PRED_GT) in getPredicateToIncImm()
1423 return PPC::getPredicate(PPC::PRED_GE, PredHint); in getPredicateToIncImm()
1424 if (PredCond == PPC::PRED_LE) in getPredicateToIncImm()
1425 return PPC::getPredicate(PPC::PRED_LT, PredHint); in getPredicateToIncImm()
1451 if (BB1 && Inst->getOpcode() == PPC::PHI && Inst->getParent() == BB2) { in getSrcVReg()
1477 (*BII).getOpcode() == PPC::BCC && in eligibleForCompareElimination()
1549 if (Inst->getParent() == &MBB && Inst->getOpcode() != PPC::PHI) in eligibleForCompareElimination()
1705 PPC::Predicate Pred = (PPC::Predicate)BI2->getOperand(0).getImm(); in eliminateRedundantCompare()
1706 NewPredicate2 = (unsigned)PPC::getSwappedPredicate(Pred); in eliminateRedundantCompare()
1824 assert(Inst->getOpcode() == PPC::PHI && in eliminateRedundantCompare()
1835 Register NewVReg = MRI->createVirtualRegister(&PPC::CRRCRegClass); in eliminateRedundantCompare()
1837 TII->get(PPC::PHI), NewVReg) in eliminateRedundantCompare()
1877 if (MI.getOpcode() != PPC::RLDICR) in emitRLDICWhenLoweringJumpTables()
1885 if (SrcMI->getOpcode() != PPC::RLDICL) in emitRLDICWhenLoweringJumpTables()
1918 MI.setDesc(TII->get(PPC::RLDIC)); in emitRLDICWhenLoweringJumpTables()
1950 if (MI.getOpcode() != PPC::RLDICR) in combineSEXTAndSHL()
1973 if (SrcMI->getOpcode() != PPC::EXTSW && in combineSEXTAndSHL()
1974 SrcMI->getOpcode() != PPC::EXTSW_32_64) in combineSEXTAndSHL()
1994 SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI) in combineSEXTAndSHL()
1995 : TII->get(PPC::EXTSWSLI_32_64), in combineSEXTAndSHL()