95                       STI.isPPC64() ? PPC::BLR8 : PPC::BLR),  in PPCInstrInfo()
614   if (!(Subtarget.isPPC64() && Subtarget.hasP9Vector() &&  in shouldReduceRegisterPressure()
672   assert((Subtarget.isPPC64() && Subtarget.hasP9Vector() &&  in generateLoadForNewConst()
1250   bool isPPC64 = Subtarget.isPPC64();  in analyzeBranch()  local
1316       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,  in analyzeBranch()
1327       Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,  in analyzeBranch()
1384     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,  in analyzeBranch()
1398     Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,  in analyzeBranch()
1464   bool isPPC64 = Subtarget.isPPC64();  in insertBranch()  local
1472                               (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :  in insertBranch()
1473                               (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);  in insertBranch()
1489                             (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :  in insertBranch()
1490                             (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);  in insertBranch()
2085     bool isPPC64 = Subtarget.isPPC64();  in onlyFoldImmediate()  local
2086     ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO;  in onlyFoldImmediate()
2166       bool isPPC64 = Subtarget.isPPC64();  in PredicateInstruction()  local
2167       MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR)  in PredicateInstruction()
2168                                       : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));  in PredicateInstruction()
2189       bool isPPC64 = Subtarget.isPPC64();  in PredicateInstruction()  local
2190       MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ)  in PredicateInstruction()
2191                                       : (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));  in PredicateInstruction()
2232     bool isPPC64 = Subtarget.isPPC64();  in PredicateInstruction()  local
2235       MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8)  in PredicateInstruction()
2239       MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n)  in PredicateInstruction()
2243       MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8)  in PredicateInstruction()
2253           .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit)  in PredicateInstruction()
2254           .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine);  in PredicateInstruction()
2385   bool isPPC64 = Subtarget.isPPC64();  in optimizeCompareInstr()  local
2401   if (isPPC64) {  in optimizeCompareInstr()
2772   if (Subtarget.isPPC64() && Opc == PPC::CMPWI)  in optimizeCmpPostRA()
3094     const int64_t Offset = Subtarget.isPPC64() ? -0x7010 : -0x7008;  in expandPostRAPseudo()
3095     const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2;  in expandPostRAPseudo()
3096     MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ));  in expandPostRAPseudo()
3178     unsigned CmpOp = Subtarget.isPPC64() ? PPC::CMPD : PPC::CMPW;  in expandPostRAPseudo()
3303   bool isPPC64 = Subtarget.isPPC64();  in materializeImmPostRA()  local
3308     BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LI8 : PPC::LI), Reg).addImm(Imm);  in materializeImmPostRA()
3310     BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LIS8 : PPC::LIS), Reg)  in materializeImmPostRA()
3313       BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg)  in materializeImmPostRA()
3317     assert(isPPC64 && "Materializing 64-bit immediate to single register is "  in materializeImmPostRA()
5170   Register SPReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;  in isTOCSaveMI()
5355   return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ));  in isBDNZ()
5392           MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR,  in createTripCountGreaterCondition()
5452   unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop);  in findLoopInstr()