Lines Matching refs:PPC
93 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
95 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
105 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
106 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
124 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
128 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
129 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
184 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
185 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
187 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
188 PPC::CRBITRCRegClass.contains(Reg); in getOperandLatency()
200 case PPC::DIR_7400: in getOperandLatency()
201 case PPC::DIR_750: in getOperandLatency()
202 case PPC::DIR_970: in getOperandLatency()
203 case PPC::DIR_E5500: in getOperandLatency()
204 case PPC::DIR_PWR4: in getOperandLatency()
205 case PPC::DIR_PWR5: in getOperandLatency()
206 case PPC::DIR_PWR5X: in getOperandLatency()
207 case PPC::DIR_PWR6: in getOperandLatency()
208 case PPC::DIR_PWR6X: in getOperandLatency()
209 case PPC::DIR_PWR7: in getOperandLatency()
210 case PPC::DIR_PWR8: in getOperandLatency()
240 case PPC::FADD: in isAssociativeAndCommutative()
241 case PPC::FADDS: in isAssociativeAndCommutative()
243 case PPC::FMUL: in isAssociativeAndCommutative()
244 case PPC::FMULS: in isAssociativeAndCommutative()
246 case PPC::VADDFP: in isAssociativeAndCommutative()
248 case PPC::XSADDDP: in isAssociativeAndCommutative()
249 case PPC::XVADDDP: in isAssociativeAndCommutative()
250 case PPC::XVADDSP: in isAssociativeAndCommutative()
251 case PPC::XSADDSP: in isAssociativeAndCommutative()
253 case PPC::XSMULDP: in isAssociativeAndCommutative()
254 case PPC::XVMULDP: in isAssociativeAndCommutative()
255 case PPC::XVMULSP: in isAssociativeAndCommutative()
256 case PPC::XSMULSP: in isAssociativeAndCommutative()
261 case PPC::MULHD: in isAssociativeAndCommutative()
262 case PPC::MULLD: in isAssociativeAndCommutative()
263 case PPC::MULHW: in isAssociativeAndCommutative()
264 case PPC::MULLW: in isAssociativeAndCommutative()
287 {PPC::XSMADDADP, PPC::XSADDDP, PPC::XSMULDP, 1, 2, PPC::XSSUBDP},
288 {PPC::XSMADDASP, PPC::XSADDSP, PPC::XSMULSP, 1, 2, PPC::XSSUBSP},
289 {PPC::XVMADDADP, PPC::XVADDDP, PPC::XVMULDP, 1, 2, PPC::XVSUBDP},
290 {PPC::XVMADDASP, PPC::XVADDSP, PPC::XVMULSP, 1, 2, PPC::XVSUBSP},
291 {PPC::FMADD, PPC::FADD, PPC::FMUL, 3, 1, PPC::FSUB},
292 {PPC::FMADDS, PPC::FADDS, PPC::FMULS, 3, 1, PPC::FSUBS}};
435 if (Opcode != PPC::XSMADDASP && Opcode != PPC::XSMADDADP) in getFMAPatterns()
578 if (Operand.getReg() == PPC::ZERO8) { in finalizeInsInstrs()
649 *MBB->getParent(), PPC::RegisterPressureSets::VSSRC); in shouldReduceRegisterPressure()
652 return GetMBBPressure(MBB)[PPC::RegisterPressureSets::VSSRC] > in shouldReduceRegisterPressure()
680 Register VReg1 = MRI->createVirtualRegister(&PPC::G8RC_and_G8RC_NOX0RegClass); in generateLoadForNewConst()
682 BuildMI(*MF, MI->getDebugLoc(), get(PPC::ADDIStocHA8), VReg1) in generateLoadForNewConst()
683 .addReg(PPC::X2) in generateLoadForNewConst()
692 LoadOpcode = PPC::DFLOADf32; in generateLoadForNewConst()
694 LoadOpcode = PPC::DFLOADf64; in generateLoadForNewConst()
1003 .addReg(PPC::ZERO8); in reassociateFMA()
1040 case PPC::EXTSW: in isCoalescableExtInstr()
1041 case PPC::EXTSW_32: in isCoalescableExtInstr()
1042 case PPC::EXTSW_32_64: in isCoalescableExtInstr()
1045 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
1072 case PPC::LI: in isReallyTriviallyReMaterializable()
1073 case PPC::LI8: in isReallyTriviallyReMaterializable()
1074 case PPC::PLI: in isReallyTriviallyReMaterializable()
1075 case PPC::PLI8: in isReallyTriviallyReMaterializable()
1076 case PPC::LIS: in isReallyTriviallyReMaterializable()
1077 case PPC::LIS8: in isReallyTriviallyReMaterializable()
1078 case PPC::ADDIStocHA: in isReallyTriviallyReMaterializable()
1079 case PPC::ADDIStocHA8: in isReallyTriviallyReMaterializable()
1080 case PPC::ADDItocL: in isReallyTriviallyReMaterializable()
1081 case PPC::LOAD_STACK_GUARD: in isReallyTriviallyReMaterializable()
1082 case PPC::XXLXORz: in isReallyTriviallyReMaterializable()
1083 case PPC::XXLXORspz: in isReallyTriviallyReMaterializable()
1084 case PPC::XXLXORdpz: in isReallyTriviallyReMaterializable()
1085 case PPC::XXLEQVOnes: in isReallyTriviallyReMaterializable()
1086 case PPC::XXSPLTI32DX: in isReallyTriviallyReMaterializable()
1087 case PPC::XXSPLTIW: in isReallyTriviallyReMaterializable()
1088 case PPC::XXSPLTIDP: in isReallyTriviallyReMaterializable()
1089 case PPC::V_SET0B: in isReallyTriviallyReMaterializable()
1090 case PPC::V_SET0H: in isReallyTriviallyReMaterializable()
1091 case PPC::V_SET0: in isReallyTriviallyReMaterializable()
1092 case PPC::V_SETALLONESB: in isReallyTriviallyReMaterializable()
1093 case PPC::V_SETALLONESH: in isReallyTriviallyReMaterializable()
1094 case PPC::V_SETALLONES: in isReallyTriviallyReMaterializable()
1095 case PPC::CRSET: in isReallyTriviallyReMaterializable()
1096 case PPC::CRUNSET: in isReallyTriviallyReMaterializable()
1097 case PPC::XXSETACCZ: in isReallyTriviallyReMaterializable()
1098 case PPC::XXSETACCZW: in isReallyTriviallyReMaterializable()
1122 if (MI.getOpcode() != PPC::RLWIMI && MI.getOpcode() != PPC::RLWIMI_rec) in commuteInstructionImpl()
1207 int AltOpc = PPC::getAltVSXFMAOpcode(MI.getOpcode()); in findCommutedOpIndices()
1223 default: Opcode = PPC::NOP; break; in insertNoop()
1224 case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break; in insertNoop()
1225 case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
1226 …case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling mod… in insertNoop()
1228 case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break; in insertNoop()
1238 Nop.setOpcode(PPC::NOP); in getNop()
1263 if (I->getOpcode() == PPC::B && in analyzeBranch()
1279 if (LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1284 } else if (LastInst.getOpcode() == PPC::BCC) { in analyzeBranch()
1292 } else if (LastInst.getOpcode() == PPC::BC) { in analyzeBranch()
1297 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
1300 } else if (LastInst.getOpcode() == PPC::BCn) { in analyzeBranch()
1305 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
1308 } else if (LastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
1309 LastInst.getOpcode() == PPC::BDNZ) { in analyzeBranch()
1316 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1319 } else if (LastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
1320 LastInst.getOpcode() == PPC::BDZ) { in analyzeBranch()
1327 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1344 if (SecondLastInst.getOpcode() == PPC::BCC && in analyzeBranch()
1345 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1354 } else if (SecondLastInst.getOpcode() == PPC::BC && in analyzeBranch()
1355 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1360 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET)); in analyzeBranch()
1364 } else if (SecondLastInst.getOpcode() == PPC::BCn && in analyzeBranch()
1365 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1370 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_UNSET)); in analyzeBranch()
1374 } else if ((SecondLastInst.getOpcode() == PPC::BDNZ8 || in analyzeBranch()
1375 SecondLastInst.getOpcode() == PPC::BDNZ) && in analyzeBranch()
1376 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1384 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1388 } else if ((SecondLastInst.getOpcode() == PPC::BDZ8 || in analyzeBranch()
1389 SecondLastInst.getOpcode() == PPC::BDZ) && in analyzeBranch()
1390 LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1398 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR, in analyzeBranch()
1406 if (SecondLastInst.getOpcode() == PPC::B && LastInst.getOpcode() == PPC::B) { in analyzeBranch()
1428 if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC && in removeBranch()
1429 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
1430 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
1431 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
1441 if (I->getOpcode() != PPC::BCC && in removeBranch()
1442 I->getOpcode() != PPC::BC && I->getOpcode() != PPC::BCn && in removeBranch()
1443 I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ && in removeBranch()
1444 I->getOpcode() != PPC::BDZ8 && I->getOpcode() != PPC::BDZ) in removeBranch()
1469 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB); in insertBranch()
1470 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1472 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1473 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1474 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
1475 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
1476 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
1477 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
1479 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
1487 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in insertBranch()
1489 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) : in insertBranch()
1490 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB); in insertBranch()
1491 else if (Cond[0].getImm() == PPC::PRED_BIT_SET) in insertBranch()
1492 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB); in insertBranch()
1493 else if (Cond[0].getImm() == PPC::PRED_BIT_UNSET) in insertBranch()
1494 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB); in insertBranch()
1496 BuildMI(&MBB, DL, get(PPC::BCC)) in insertBranch()
1500 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB); in insertBranch()
1518 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8) in canInsertSelect()
1534 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1535 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1536 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1537 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1565 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
1566 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
1568 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1569 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1572 unsigned OpCode = Is64Bit ? PPC::ISEL8 : PPC::ISEL; in insertSelect()
1573 auto SelectPred = static_cast<PPC::Predicate>(Cond[0].getImm()); in insertSelect()
1578 case PPC::PRED_EQ: in insertSelect()
1579 case PPC::PRED_EQ_MINUS: in insertSelect()
1580 case PPC::PRED_EQ_PLUS: in insertSelect()
1581 SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
1582 case PPC::PRED_NE: in insertSelect()
1583 case PPC::PRED_NE_MINUS: in insertSelect()
1584 case PPC::PRED_NE_PLUS: in insertSelect()
1585 SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
1586 case PPC::PRED_LT: in insertSelect()
1587 case PPC::PRED_LT_MINUS: in insertSelect()
1588 case PPC::PRED_LT_PLUS: in insertSelect()
1589 SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
1590 case PPC::PRED_GE: in insertSelect()
1591 case PPC::PRED_GE_MINUS: in insertSelect()
1592 case PPC::PRED_GE_PLUS: in insertSelect()
1593 SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
1594 case PPC::PRED_GT: in insertSelect()
1595 case PPC::PRED_GT_MINUS: in insertSelect()
1596 case PPC::PRED_GT_PLUS: in insertSelect()
1597 SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
1598 case PPC::PRED_LE: in insertSelect()
1599 case PPC::PRED_LE_MINUS: in insertSelect()
1600 case PPC::PRED_LE_PLUS: in insertSelect()
1601 SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
1602 case PPC::PRED_UN: in insertSelect()
1603 case PPC::PRED_UN_MINUS: in insertSelect()
1604 case PPC::PRED_UN_PLUS: in insertSelect()
1605 SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
1606 case PPC::PRED_NU: in insertSelect()
1607 case PPC::PRED_NU_MINUS: in insertSelect()
1608 case PPC::PRED_NU_PLUS: in insertSelect()
1609 SubIdx = PPC::sub_un; SwapOps = true; break; in insertSelect()
1610 case PPC::PRED_BIT_SET: SubIdx = 0; SwapOps = false; break; in insertSelect()
1611 case PPC::PRED_BIT_UNSET: SubIdx = 0; SwapOps = true; break; in insertSelect()
1620 if (MRI.getRegClass(FirstReg)->contains(PPC::R0) || in insertSelect()
1621 MRI.getRegClass(FirstReg)->contains(PPC::X0)) { in insertSelect()
1623 MRI.getRegClass(FirstReg)->contains(PPC::X0) ? in insertSelect()
1624 &PPC::G8RC_NOX0RegClass : &PPC::GPRC_NOR0RegClass; in insertSelect()
1638 if (CRBit == PPC::CR0LT || CRBit == PPC::CR1LT || in getCRBitValue()
1639 CRBit == PPC::CR2LT || CRBit == PPC::CR3LT || in getCRBitValue()
1640 CRBit == PPC::CR4LT || CRBit == PPC::CR5LT || in getCRBitValue()
1641 CRBit == PPC::CR6LT || CRBit == PPC::CR7LT) in getCRBitValue()
1643 if (CRBit == PPC::CR0GT || CRBit == PPC::CR1GT || in getCRBitValue()
1644 CRBit == PPC::CR2GT || CRBit == PPC::CR3GT || in getCRBitValue()
1645 CRBit == PPC::CR4GT || CRBit == PPC::CR5GT || in getCRBitValue()
1646 CRBit == PPC::CR6GT || CRBit == PPC::CR7GT) in getCRBitValue()
1648 if (CRBit == PPC::CR0EQ || CRBit == PPC::CR1EQ || in getCRBitValue()
1649 CRBit == PPC::CR2EQ || CRBit == PPC::CR3EQ || in getCRBitValue()
1650 CRBit == PPC::CR4EQ || CRBit == PPC::CR5EQ || in getCRBitValue()
1651 CRBit == PPC::CR6EQ || CRBit == PPC::CR7EQ) in getCRBitValue()
1653 if (CRBit == PPC::CR0UN || CRBit == PPC::CR1UN || in getCRBitValue()
1654 CRBit == PPC::CR2UN || CRBit == PPC::CR3UN || in getCRBitValue()
1655 CRBit == PPC::CR4UN || CRBit == PPC::CR5UN || in getCRBitValue()
1656 CRBit == PPC::CR6UN || CRBit == PPC::CR7UN) in getCRBitValue()
1670 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
1671 PPC::VSRCRegClass.contains(SrcReg)) { in copyPhysReg()
1673 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
1679 } else if (PPC::F8RCRegClass.contains(SrcReg) && in copyPhysReg()
1680 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
1682 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
1691 if (PPC::CRBITRCRegClass.contains(SrcReg) && in copyPhysReg()
1692 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
1694 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg()
1698 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg) in copyPhysReg()
1704 } else if (PPC::CRRCRegClass.contains(SrcReg) && in copyPhysReg()
1705 (PPC::G8RCRegClass.contains(DestReg) || in copyPhysReg()
1706 PPC::GPRCRegClass.contains(DestReg))) { in copyPhysReg()
1707 bool Is64Bit = PPC::G8RCRegClass.contains(DestReg); in copyPhysReg()
1708 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF; in copyPhysReg()
1709 unsigned ShCode = Is64Bit ? PPC::RLWINM8 : PPC::RLWINM; in copyPhysReg()
1722 } else if (PPC::G8RCRegClass.contains(SrcReg) && in copyPhysReg()
1723 PPC::VSFRCRegClass.contains(DestReg)) { in copyPhysReg()
1726 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
1730 } else if (PPC::VSFRCRegClass.contains(SrcReg) && in copyPhysReg()
1731 PPC::G8RCRegClass.contains(DestReg)) { in copyPhysReg()
1734 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg); in copyPhysReg()
1737 } else if (PPC::SPERCRegClass.contains(SrcReg) && in copyPhysReg()
1738 PPC::GPRCRegClass.contains(DestReg)) { in copyPhysReg()
1739 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg); in copyPhysReg()
1742 } else if (PPC::GPRCRegClass.contains(SrcReg) && in copyPhysReg()
1743 PPC::SPERCRegClass.contains(DestReg)) { in copyPhysReg()
1744 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg); in copyPhysReg()
1750 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1751 Opc = PPC::OR; in copyPhysReg()
1752 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1753 Opc = PPC::OR8; in copyPhysReg()
1754 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1755 Opc = PPC::FMR; in copyPhysReg()
1756 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1757 Opc = PPC::MCRF; in copyPhysReg()
1758 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1759 Opc = PPC::VOR; in copyPhysReg()
1760 else if (PPC::VSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1769 Opc = PPC::XXLOR; in copyPhysReg()
1770 else if (PPC::VSFRCRegClass.contains(DestReg, SrcReg) || in copyPhysReg()
1771 PPC::VSSRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1772 Opc = (Subtarget.hasP9Vector()) ? PPC::XSCPSGNDP : PPC::XXLORf; in copyPhysReg()
1774 PPC::VSRpRCRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
1775 if (SrcReg > PPC::VSRp15) in copyPhysReg()
1776 SrcReg = PPC::V0 + (SrcReg - PPC::VSRp16) * 2; in copyPhysReg()
1778 SrcReg = PPC::VSL0 + (SrcReg - PPC::VSRp0) * 2; in copyPhysReg()
1779 if (DestReg > PPC::VSRp15) in copyPhysReg()
1780 DestReg = PPC::V0 + (DestReg - PPC::VSRp16) * 2; in copyPhysReg()
1782 DestReg = PPC::VSL0 + (DestReg - PPC::VSRp0) * 2; in copyPhysReg()
1783 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg). in copyPhysReg()
1785 BuildMI(MBB, I, DL, get(PPC::XXLOR), DestReg + 1). in copyPhysReg()
1789 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1790 Opc = PPC::CROR; in copyPhysReg()
1791 else if (PPC::SPERCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
1792 Opc = PPC::EVOR; in copyPhysReg()
1793 else if ((PPC::ACCRCRegClass.contains(DestReg) || in copyPhysReg()
1794 PPC::UACCRCRegClass.contains(DestReg)) && in copyPhysReg()
1795 (PPC::ACCRCRegClass.contains(SrcReg) || in copyPhysReg()
1796 PPC::UACCRCRegClass.contains(SrcReg))) { in copyPhysReg()
1802 bool DestPrimed = PPC::ACCRCRegClass.contains(DestReg); in copyPhysReg()
1803 bool SrcPrimed = PPC::ACCRCRegClass.contains(SrcReg); in copyPhysReg()
1805 PPC::VSL0 + (SrcReg - (SrcPrimed ? PPC::ACC0 : PPC::UACC0)) * 4; in copyPhysReg()
1807 PPC::VSL0 + (DestReg - (DestPrimed ? PPC::ACC0 : PPC::UACC0)) * 4; in copyPhysReg()
1809 BuildMI(MBB, I, DL, get(PPC::XXMFACC), SrcReg).addReg(SrcReg); in copyPhysReg()
1811 BuildMI(MBB, I, DL, get(PPC::XXLOR), VSLDestReg + Idx) in copyPhysReg()
1815 BuildMI(MBB, I, DL, get(PPC::XXMTACC), DestReg).addReg(DestReg); in copyPhysReg()
1817 BuildMI(MBB, I, DL, get(PPC::XXMTACC), SrcReg).addReg(SrcReg); in copyPhysReg()
1819 } else if (PPC::G8pRCRegClass.contains(DestReg) && in copyPhysReg()
1820 PPC::G8pRCRegClass.contains(SrcReg)) { in copyPhysReg()
1822 unsigned DestRegIdx = DestReg - PPC::G8p0; in copyPhysReg()
1823 MCRegister DestRegSub0 = PPC::X0 + 2 * DestRegIdx; in copyPhysReg()
1824 MCRegister DestRegSub1 = PPC::X0 + 2 * DestRegIdx + 1; in copyPhysReg()
1825 unsigned SrcRegIdx = SrcReg - PPC::G8p0; in copyPhysReg()
1826 MCRegister SrcRegSub0 = PPC::X0 + 2 * SrcRegIdx; in copyPhysReg()
1827 MCRegister SrcRegSub1 = PPC::X0 + 2 * SrcRegIdx + 1; in copyPhysReg()
1828 BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub0) in copyPhysReg()
1831 BuildMI(MBB, I, DL, get(PPC::OR8), DestRegSub1) in copyPhysReg()
1849 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1850 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1852 } else if (PPC::G8RCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1853 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
1855 } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1857 } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1859 } else if (PPC::SPERCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1861 } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1863 } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1865 } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1867 } else if (PPC::VSRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1869 } else if (PPC::VSFRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1871 } else if (PPC::VSSRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1873 } else if (PPC::SPILLTOVSRRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1875 } else if (PPC::ACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1879 } else if (PPC::UACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1883 } else if (PPC::WACCRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1887 } else if (PPC::VSRpRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1891 } else if (PPC::G8pRCRegClass.hasSubClassEq(RC)) { in getSpillIndex()
1925 if (PPC::CRRCRegClass.hasSubClassEq(RC) || in StoreRegToStackSlot()
1926 PPC::CRBITRCRegClass.hasSubClassEq(RC)) in StoreRegToStackSlot()
2021 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR) in reverseBranchCondition()
2025 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in reverseBranchCondition()
2036 if (DefOpc != PPC::LI && DefOpc != PPC::LI8) in onlyFoldImmediate()
2072 if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && in onlyFoldImmediate()
2073 UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) in onlyFoldImmediate()
2086 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2088 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2089 PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2113 if (MI.definesRegister(PPC::CTR) || MI.definesRegister(PPC::CTR8)) in MBBDefinesCTR()
2153 case PPC::MFFS: in isSchedulingBoundary()
2154 case PPC::MTFSF: in isSchedulingBoundary()
2155 case PPC::FENCE: in isSchedulingBoundary()
2164 if (OpC == PPC::BLR || OpC == PPC::BLR8) { in PredicateInstruction()
2165 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2167 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
2168 : (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR))); in PredicateInstruction()
2173 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2174 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
2176 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2177 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
2180 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
2187 } else if (OpC == PPC::B) { in PredicateInstruction()
2188 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) { in PredicateInstruction()
2190 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
2191 : (isPPC64 ? PPC::BDZ8 : PPC::BDZ))); in PredicateInstruction()
2196 } else if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2200 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2204 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2208 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2216 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2224 } else if (OpC == PPC::BCTR || OpC == PPC::BCTR8 || OpC == PPC::BCTRL || in PredicateInstruction()
2225 OpC == PPC::BCTRL8 || OpC == PPC::BCTRL_RM || in PredicateInstruction()
2226 OpC == PPC::BCTRL8_RM) { in PredicateInstruction()
2227 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) in PredicateInstruction()
2230 bool setLR = OpC == PPC::BCTRL || OpC == PPC::BCTRL8 || in PredicateInstruction()
2231 OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM; in PredicateInstruction()
2234 if (Pred[0].getImm() == PPC::PRED_BIT_SET) { in PredicateInstruction()
2235 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
2236 : (setLR ? PPC::BCCTRL : PPC::BCCTR))); in PredicateInstruction()
2238 } else if (Pred[0].getImm() == PPC::PRED_BIT_UNSET) { in PredicateInstruction()
2239 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
2240 : (setLR ? PPC::BCCTRLn : PPC::BCCTRn))); in PredicateInstruction()
2243 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCCTRL8 : PPC::BCCCTR8) in PredicateInstruction()
2244 : (setLR ? PPC::BCCCTRL : PPC::BCCCTR))); in PredicateInstruction()
2253 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::Implicit) in PredicateInstruction()
2254 .addReg(isPPC64 ? PPC::LR8 : PPC::LR, RegState::ImplicitDefine); in PredicateInstruction()
2255 if (OpC == PPC::BCTRL_RM || OpC == PPC::BCTRL8_RM) in PredicateInstruction()
2257 .addReg(PPC::RM, RegState::ImplicitDefine); in PredicateInstruction()
2270 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR) in SubsumesPredicate()
2272 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR) in SubsumesPredicate()
2279 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm(); in SubsumesPredicate()
2280 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm(); in SubsumesPredicate()
2286 if (P1 == PPC::PRED_LE && in SubsumesPredicate()
2287 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
2289 if (P1 == PPC::PRED_GE && in SubsumesPredicate()
2290 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ)) in SubsumesPredicate()
2306 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass, in ClobbersPredicate()
2307 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass }; in ClobbersPredicate()
2338 case PPC::CMPWI: in analyzeCompare()
2339 case PPC::CMPLWI: in analyzeCompare()
2340 case PPC::CMPDI: in analyzeCompare()
2341 case PPC::CMPLDI: in analyzeCompare()
2347 case PPC::CMPW: in analyzeCompare()
2348 case PPC::CMPLW: in analyzeCompare()
2349 case PPC::CMPD: in analyzeCompare()
2350 case PPC::CMPLD: in analyzeCompare()
2351 case PPC::FCMPUS: in analyzeCompare()
2352 case PPC::FCMPUD: in analyzeCompare()
2373 if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD) in optimizeCompareInstr()
2386 bool is32BitSignedCompare = OpC == PPC::CMPWI || OpC == PPC::CMPW; in optimizeCompareInstr()
2387 bool is32BitUnsignedCompare = OpC == PPC::CMPLWI || OpC == PPC::CMPLW; in optimizeCompareInstr()
2388 bool is64BitUnsignedCompare = OpC == PPC::CMPLDI || OpC == PPC::CMPLD; in optimizeCompareInstr()
2428 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
2429 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2430 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2432 if (PredCond != PPC::PRED_EQ && PredCond != PPC::PRED_NE) in optimizeCompareInstr()
2434 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
2435 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
2437 if (SubIdx != PPC::sub_eq) in optimizeCompareInstr()
2462 SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate; in optimizeCompareInstr()
2491 if (UseMI->getOpcode() != PPC::BCC) in optimizeCompareInstr()
2494 PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2495 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2496 unsigned PredHint = PPC::getPredicateHint(Pred); in optimizeCompareInstr()
2501 if (Immed == -1 && PredCond == PPC::PRED_GT) in optimizeCompareInstr()
2504 Pred = PPC::getPredicate(PPC::PRED_GE, PredHint); in optimizeCompareInstr()
2505 else if (Immed == -1 && PredCond == PPC::PRED_LE) in optimizeCompareInstr()
2507 Pred = PPC::getPredicate(PPC::PRED_LT, PredHint); in optimizeCompareInstr()
2508 else if (Immed == 1 && PredCond == PPC::PRED_LT) in optimizeCompareInstr()
2510 Pred = PPC::getPredicate(PPC::PRED_LE, PredHint); in optimizeCompareInstr()
2511 else if (Immed == 1 && PredCond == PPC::PRED_GE) in optimizeCompareInstr()
2513 Pred = PPC::getPredicate(PPC::PRED_GT, PredHint); in optimizeCompareInstr()
2535 if (&*I != &CmpInstr && (Instr.modifiesRegister(PPC::CR0, TRI) || in optimizeCompareInstr()
2536 Instr.readsRegister(PPC::CR0, TRI))) in optimizeCompareInstr()
2545 if ((OpC == PPC::CMPW || OpC == PPC::CMPLW || in optimizeCompareInstr()
2546 OpC == PPC::CMPD || OpC == PPC::CMPLD) && in optimizeCompareInstr()
2547 (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) && in optimizeCompareInstr()
2570 if (MIOpC == PPC::ANDI_rec || MIOpC == PPC::ANDI8_rec || in optimizeCompareInstr()
2571 MIOpC == PPC::ANDIS_rec || MIOpC == PPC::ANDIS8_rec) in optimizeCompareInstr()
2574 NewOpC = PPC::getRecordFormOpcode(MIOpC); in optimizeCompareInstr()
2575 if (NewOpC == -1 && PPC::getNonRecordFormOpcode(MIOpC) != -1) in optimizeCompareInstr()
2592 if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) && in optimizeCompareInstr()
2617 if (UseMI->getOpcode() == PPC::BCC) { in optimizeCompareInstr()
2618 PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm(); in optimizeCompareInstr()
2619 unsigned PredCond = PPC::getPredicateCondition(Pred); in optimizeCompareInstr()
2621 PredCond == PPC::PRED_EQ || PredCond == PPC::PRED_NE) && in optimizeCompareInstr()
2625 PPC::getSwappedPredicate(Pred))); in optimizeCompareInstr()
2626 } else if (UseMI->getOpcode() == PPC::ISEL || in optimizeCompareInstr()
2627 UseMI->getOpcode() == PPC::ISEL8) { in optimizeCompareInstr()
2629 assert((!equalityOnly || NewSubReg == PPC::sub_eq) && in optimizeCompareInstr()
2632 if (NewSubReg == PPC::sub_lt) in optimizeCompareInstr()
2633 NewSubReg = PPC::sub_gt; in optimizeCompareInstr()
2634 else if (NewSubReg == PPC::sub_gt) in optimizeCompareInstr()
2635 NewSubReg = PPC::sub_lt; in optimizeCompareInstr()
2654 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0); in optimizeCompareInstr()
2658 MI->clearRegisterDeads(PPC::CR0); in optimizeCompareInstr()
2670 if (MIOpC == PPC::RLWINM || MIOpC == PPC::RLWINM8) { in optimizeCompareInstr()
2685 NewOpC = MIOpC == PPC::RLWINM in optimizeCompareInstr()
2686 ? (MBInLoHWord ? PPC::ANDI_rec : PPC::ANDIS_rec) in optimizeCompareInstr()
2687 : (MBInLoHWord ? PPC::ANDI8_rec : PPC::ANDIS8_rec); in optimizeCompareInstr()
2695 NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDIS_rec : PPC::ANDIS8_rec; in optimizeCompareInstr()
2704 } else if (MIOpC == PPC::RLDICL && MI->getOperand(2).getImm() == 0) { in optimizeCompareInstr()
2708 NewOpC = PPC::ANDI8_rec; in optimizeCompareInstr()
2731 assert(MI->definesRegister(PPC::CR0) && in optimizeCompareInstr()
2765 if (Opc == PPC::CMPLWI || Opc == PPC::CMPLDI) in optimizeCmpPostRA()
2772 if (Subtarget.isPPC64() && Opc == PPC::CMPWI) in optimizeCmpPostRA()
2786 if (CRReg != PPC::CR0) in optimizeCmpPostRA()
2798 int NewOpC = PPC::getRecordFormOpcode(SrcMIOpc); in optimizeCmpPostRA()
2811 assert(SrcMI->definesRegister(PPC::CR0) && in optimizeCmpPostRA()
2858 case PPC::STD: in isClusterableLdStOpcPair()
2859 case PPC::STFD: in isClusterableLdStOpcPair()
2860 case PPC::STXSD: in isClusterableLdStOpcPair()
2861 case PPC::DFSTOREf64: in isClusterableLdStOpcPair()
2866 case PPC::STW: in isClusterableLdStOpcPair()
2867 case PPC::STW8: in isClusterableLdStOpcPair()
2868 return SecondOpc == PPC::STW || SecondOpc == PPC::STW8; in isClusterableLdStOpcPair()
2935 if (Opcode == PPC::INLINEASM || Opcode == PPC::INLINEASM_BR) { in getInstSizeInBytes()
2998 case PPC::DFLOADf32: in expandVSXMemPseudo()
2999 UpperOpcode = PPC::LXSSP; in expandVSXMemPseudo()
3000 LowerOpcode = PPC::LFS; in expandVSXMemPseudo()
3002 case PPC::DFLOADf64: in expandVSXMemPseudo()
3003 UpperOpcode = PPC::LXSD; in expandVSXMemPseudo()
3004 LowerOpcode = PPC::LFD; in expandVSXMemPseudo()
3006 case PPC::DFSTOREf32: in expandVSXMemPseudo()
3007 UpperOpcode = PPC::STXSSP; in expandVSXMemPseudo()
3008 LowerOpcode = PPC::STFS; in expandVSXMemPseudo()
3010 case PPC::DFSTOREf64: in expandVSXMemPseudo()
3011 UpperOpcode = PPC::STXSD; in expandVSXMemPseudo()
3012 LowerOpcode = PPC::STFD; in expandVSXMemPseudo()
3014 case PPC::XFLOADf32: in expandVSXMemPseudo()
3015 UpperOpcode = PPC::LXSSPX; in expandVSXMemPseudo()
3016 LowerOpcode = PPC::LFSX; in expandVSXMemPseudo()
3018 case PPC::XFLOADf64: in expandVSXMemPseudo()
3019 UpperOpcode = PPC::LXSDX; in expandVSXMemPseudo()
3020 LowerOpcode = PPC::LFDX; in expandVSXMemPseudo()
3022 case PPC::XFSTOREf32: in expandVSXMemPseudo()
3023 UpperOpcode = PPC::STXSSPX; in expandVSXMemPseudo()
3024 LowerOpcode = PPC::STFSX; in expandVSXMemPseudo()
3026 case PPC::XFSTOREf64: in expandVSXMemPseudo()
3027 UpperOpcode = PPC::STXSDX; in expandVSXMemPseudo()
3028 LowerOpcode = PPC::STFDX; in expandVSXMemPseudo()
3030 case PPC::LIWAX: in expandVSXMemPseudo()
3031 UpperOpcode = PPC::LXSIWAX; in expandVSXMemPseudo()
3032 LowerOpcode = PPC::LFIWAX; in expandVSXMemPseudo()
3034 case PPC::LIWZX: in expandVSXMemPseudo()
3035 UpperOpcode = PPC::LXSIWZX; in expandVSXMemPseudo()
3036 LowerOpcode = PPC::LFIWZX; in expandVSXMemPseudo()
3038 case PPC::STIWX: in expandVSXMemPseudo()
3039 UpperOpcode = PPC::STXSIWX; in expandVSXMemPseudo()
3040 LowerOpcode = PPC::STFIWX; in expandVSXMemPseudo()
3048 if ((TargetReg >= PPC::F0 && TargetReg <= PPC::F31) || in expandVSXMemPseudo()
3049 (TargetReg >= PPC::VSL0 && TargetReg <= PPC::VSL31)) in expandVSXMemPseudo()
3066 case PPC::BUILD_UACC: { in expandPostRAPseudo()
3069 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) { in expandPostRAPseudo()
3070 MCRegister SrcVSR = PPC::VSL0 + (UACC - PPC::UACC0) * 4; in expandPostRAPseudo()
3071 MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4; in expandPostRAPseudo()
3076 BuildMI(MBB, MI, DL, get(PPC::XXLOR), DstVSR + VecNo) in expandPostRAPseudo()
3085 case PPC::KILL_PAIR: { in expandPostRAPseudo()
3086 MI.setDesc(get(PPC::UNENCODED_NOP)); in expandPostRAPseudo()
3095 const unsigned Reg = Subtarget.isPPC64() ? PPC::X13 : PPC::R2; in expandPostRAPseudo()
3096 MI.setDesc(get(Subtarget.isPPC64() ? PPC::LD : PPC::LWZ)); in expandPostRAPseudo()
3102 case PPC::DFLOADf32: in expandPostRAPseudo()
3103 case PPC::DFLOADf64: in expandPostRAPseudo()
3104 case PPC::DFSTOREf32: in expandPostRAPseudo()
3105 case PPC::DFSTOREf64: { in expandPostRAPseudo()
3113 case PPC::XFLOADf32: in expandPostRAPseudo()
3114 case PPC::XFSTOREf32: in expandPostRAPseudo()
3115 case PPC::LIWAX: in expandPostRAPseudo()
3116 case PPC::LIWZX: in expandPostRAPseudo()
3117 case PPC::STIWX: { in expandPostRAPseudo()
3124 case PPC::XFLOADf64: in expandPostRAPseudo()
3125 case PPC::XFSTOREf64: { in expandPostRAPseudo()
3132 case PPC::SPILLTOVSR_LD: { in expandPostRAPseudo()
3134 if (PPC::VSFRCRegClass.contains(TargetReg)) { in expandPostRAPseudo()
3135 MI.setDesc(get(PPC::DFLOADf64)); in expandPostRAPseudo()
3139 MI.setDesc(get(PPC::LD)); in expandPostRAPseudo()
3142 case PPC::SPILLTOVSR_ST: { in expandPostRAPseudo()
3144 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
3146 MI.setDesc(get(PPC::DFSTOREf64)); in expandPostRAPseudo()
3150 MI.setDesc(get(PPC::STD)); in expandPostRAPseudo()
3154 case PPC::SPILLTOVSR_LDX: { in expandPostRAPseudo()
3156 if (PPC::VSFRCRegClass.contains(TargetReg)) in expandPostRAPseudo()
3157 MI.setDesc(get(PPC::LXSDX)); in expandPostRAPseudo()
3159 MI.setDesc(get(PPC::LDX)); in expandPostRAPseudo()
3162 case PPC::SPILLTOVSR_STX: { in expandPostRAPseudo()
3164 if (PPC::VSFRCRegClass.contains(SrcReg)) { in expandPostRAPseudo()
3166 MI.setDesc(get(PPC::STXSDX)); in expandPostRAPseudo()
3169 MI.setDesc(get(PPC::STDX)); in expandPostRAPseudo()
3175 case PPC::CFENCE: in expandPostRAPseudo()
3176 case PPC::CFENCE8: { in expandPostRAPseudo()
3178 unsigned CmpOp = Subtarget.isPPC64() ? PPC::CMPD : PPC::CMPW; in expandPostRAPseudo()
3179 BuildMI(MBB, MI, DL, get(CmpOp), PPC::CR7).addReg(Val).addReg(Val); in expandPostRAPseudo()
3180 BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP)) in expandPostRAPseudo()
3181 .addImm(PPC::PRED_NE_MINUS) in expandPostRAPseudo()
3182 .addReg(PPC::CR7) in expandPostRAPseudo()
3184 MI.setDesc(get(PPC::ISYNC)); in expandPostRAPseudo()
3200 if (CompareOpc == PPC::CMPWI || CompareOpc == PPC::CMPDI) { in selectReg()
3203 case PPC::sub_lt: in selectReg()
3205 case PPC::sub_gt: in selectReg()
3207 case PPC::sub_eq: in selectReg()
3212 else if (CompareOpc == PPC::CMPLWI || CompareOpc == PPC::CMPLDI) { in selectReg()
3215 case PPC::sub_lt: in selectReg()
3217 case PPC::sub_gt: in selectReg()
3219 case PPC::sub_eq: in selectReg()
3223 return PPC::NoRegister; in selectReg()
3266 MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); in replaceInstrWithLI()
3269 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); in replaceInstrWithLI()
3273 MI.setDesc(get(LII.Is64Bit ? PPC::LI8 : PPC::LI)); in replaceInstrWithLI()
3308 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LI8 : PPC::LI), Reg).addImm(Imm); in materializeImmPostRA()
3310 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::LIS8 : PPC::LIS), Reg) in materializeImmPostRA()
3313 BuildMI(MBB, MBBI, DL, get(isPPC64 ? PPC::ORI8 : PPC::ORI), Reg) in materializeImmPostRA()
3319 BuildMI(MBB, MBBI, DL, get(PPC::LIS8), Reg).addImm(Imm >> 48); in materializeImmPostRA()
3321 BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg) in materializeImmPostRA()
3324 BuildMI(MBB, MBBI, DL, get(PPC::RLDICR), Reg) in materializeImmPostRA()
3328 BuildMI(MBB, MBBI, DL, get(PPC::ORIS8), Reg) in materializeImmPostRA()
3332 BuildMI(MBB, MBBI, DL, get(PPC::ORI8), Reg) in materializeImmPostRA()
3359 if (DefMIForTrueReg->getOpcode() == PPC::LI || in getForwardingDefMI()
3360 DefMIForTrueReg->getOpcode() == PPC::LI8 || in getForwardingDefMI()
3361 DefMIForTrueReg->getOpcode() == PPC::ADDI || in getForwardingDefMI()
3362 DefMIForTrueReg->getOpcode() == PPC::ADDI8) { in getForwardingDefMI()
3369 if (DefMI->getOpcode() == PPC::LI || DefMI->getOpcode() == PPC::LI8) in getForwardingDefMI()
3381 Opc == PPC::CMPWI || Opc == PPC::CMPLWI || Opc == PPC::CMPDI || in getForwardingDefMI()
3382 Opc == PPC::CMPLDI || Opc == PPC::ADDI || Opc == PPC::ADDI8 || in getForwardingDefMI()
3383 Opc == PPC::ORI || Opc == PPC::ORI8 || Opc == PPC::XORI || in getForwardingDefMI()
3384 Opc == PPC::XORI8 || Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec || in getForwardingDefMI()
3385 Opc == PPC::RLDICL_32 || Opc == PPC::RLDICL_32_64 || in getForwardingDefMI()
3386 Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8 || in getForwardingDefMI()
3387 Opc == PPC::RLWINM8_rec; in getForwardingDefMI()
3389 ? PPC::isVFRegister(MI.getOperand(0).getReg()) in getForwardingDefMI()
3395 if ((Opc == PPC::OR || Opc == PPC::OR8) && in getForwardingDefMI()
3412 case PPC::LI: in getForwardingDefMI()
3413 case PPC::LI8: in getForwardingDefMI()
3414 case PPC::ADDItocL: in getForwardingDefMI()
3415 case PPC::ADDI: in getForwardingDefMI()
3416 case PPC::ADDI8: in getForwardingDefMI()
3527 (ScaleReg == PPC::R0 || ScaleReg == PPC::X0)) in foldFrameOffset()
3570 if (Opc != PPC::ADDI && Opc != PPC::ADDI8) in isADDIInstrEligibleForFolding()
3586 return Opc == PPC::ADD4 || Opc == PPC::ADD8; in isADDInstrEligibleForFolding()
3603 if (XFormOpcode == PPC::INSTRUCTION_LIST_END) in isImmInstrEligibleForFolding()
3608 PPC::isVFRegister(MI.getOperand(0).getReg()), III, true)) in isImmInstrEligibleForFolding()
3708 PPC::INSTRUCTION_LIST_END && in convertToImmediateForm()
3714 ? PPC::isVFRegister(MI.getOperand(0).getReg()) in convertToImmediateForm()
3746 if (SrcMI->getOpcode() != PPC::RLWINM && in combineRLWINM()
3747 SrcMI->getOpcode() != PPC::RLWINM_rec && in combineRLWINM()
3748 SrcMI->getOpcode() != PPC::RLWINM8 && in combineRLWINM()
3749 SrcMI->getOpcode() != PPC::RLWINM8_rec) in combineRLWINM()
3806 (MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec); in combineRLWINM()
3811 if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM8) { in combineRLWINM()
3817 MI.setDesc(get(Is64Bit ? PPC::LI8 : PPC::LI)); in combineRLWINM()
3823 MI.setDesc(get(Is64Bit ? PPC::ANDI8_rec : PPC::ANDI_rec)); in combineRLWINM()
3890 case PPC::ADD4: in instrHasImmForm()
3891 case PPC::ADD8: in instrHasImmForm()
3897 III.ImmOpcode = Opc == PPC::ADD4 ? PPC::ADDI : PPC::ADDI8; in instrHasImmForm()
3899 case PPC::ADDC: in instrHasImmForm()
3900 case PPC::ADDC8: in instrHasImmForm()
3906 III.ImmOpcode = Opc == PPC::ADDC ? PPC::ADDIC : PPC::ADDIC8; in instrHasImmForm()
3908 case PPC::ADDC_rec: in instrHasImmForm()
3914 III.ImmOpcode = PPC::ADDIC_rec; in instrHasImmForm()
3916 case PPC::SUBFC: in instrHasImmForm()
3917 case PPC::SUBFC8: in instrHasImmForm()
3922 III.ImmOpcode = Opc == PPC::SUBFC ? PPC::SUBFIC : PPC::SUBFIC8; in instrHasImmForm()
3924 case PPC::CMPW: in instrHasImmForm()
3925 case PPC::CMPD: in instrHasImmForm()
3930 III.ImmOpcode = Opc == PPC::CMPW ? PPC::CMPWI : PPC::CMPDI; in instrHasImmForm()
3932 case PPC::CMPLW: in instrHasImmForm()
3933 case PPC::CMPLD: in instrHasImmForm()
3938 III.ImmOpcode = Opc == PPC::CMPLW ? PPC::CMPLWI : PPC::CMPLDI; in instrHasImmForm()
3940 case PPC::AND_rec: in instrHasImmForm()
3941 case PPC::AND8_rec: in instrHasImmForm()
3942 case PPC::OR: in instrHasImmForm()
3943 case PPC::OR8: in instrHasImmForm()
3944 case PPC::XOR: in instrHasImmForm()
3945 case PPC::XOR8: in instrHasImmForm()
3952 case PPC::AND_rec: in instrHasImmForm()
3953 III.ImmOpcode = PPC::ANDI_rec; in instrHasImmForm()
3955 case PPC::AND8_rec: in instrHasImmForm()
3956 III.ImmOpcode = PPC::ANDI8_rec; in instrHasImmForm()
3958 case PPC::OR: III.ImmOpcode = PPC::ORI; break; in instrHasImmForm()
3959 case PPC::OR8: III.ImmOpcode = PPC::ORI8; break; in instrHasImmForm()
3960 case PPC::XOR: III.ImmOpcode = PPC::XORI; break; in instrHasImmForm()
3961 case PPC::XOR8: III.ImmOpcode = PPC::XORI8; break; in instrHasImmForm()
3964 case PPC::RLWNM: in instrHasImmForm()
3965 case PPC::RLWNM8: in instrHasImmForm()
3966 case PPC::RLWNM_rec: in instrHasImmForm()
3967 case PPC::RLWNM8_rec: in instrHasImmForm()
3968 case PPC::SLW: in instrHasImmForm()
3969 case PPC::SLW8: in instrHasImmForm()
3970 case PPC::SLW_rec: in instrHasImmForm()
3971 case PPC::SLW8_rec: in instrHasImmForm()
3972 case PPC::SRW: in instrHasImmForm()
3973 case PPC::SRW8: in instrHasImmForm()
3974 case PPC::SRW_rec: in instrHasImmForm()
3975 case PPC::SRW8_rec: in instrHasImmForm()
3976 case PPC::SRAW: in instrHasImmForm()
3977 case PPC::SRAW_rec: in instrHasImmForm()
3987 if (Opc == PPC::RLWNM || Opc == PPC::RLWNM8 || Opc == PPC::RLWNM_rec || in instrHasImmForm()
3988 Opc == PPC::RLWNM8_rec) in instrHasImmForm()
3994 case PPC::RLWNM: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
3995 case PPC::RLWNM8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
3996 case PPC::RLWNM_rec: in instrHasImmForm()
3997 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
3999 case PPC::RLWNM8_rec: in instrHasImmForm()
4000 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4002 case PPC::SLW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
4003 case PPC::SLW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
4004 case PPC::SLW_rec: in instrHasImmForm()
4005 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
4007 case PPC::SLW8_rec: in instrHasImmForm()
4008 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4010 case PPC::SRW: III.ImmOpcode = PPC::RLWINM; break; in instrHasImmForm()
4011 case PPC::SRW8: III.ImmOpcode = PPC::RLWINM8; break; in instrHasImmForm()
4012 case PPC::SRW_rec: in instrHasImmForm()
4013 III.ImmOpcode = PPC::RLWINM_rec; in instrHasImmForm()
4015 case PPC::SRW8_rec: in instrHasImmForm()
4016 III.ImmOpcode = PPC::RLWINM8_rec; in instrHasImmForm()
4018 case PPC::SRAW: in instrHasImmForm()
4021 III.ImmOpcode = PPC::SRAWI; in instrHasImmForm()
4023 case PPC::SRAW_rec: in instrHasImmForm()
4026 III.ImmOpcode = PPC::SRAWI_rec; in instrHasImmForm()
4030 case PPC::RLDCL: in instrHasImmForm()
4031 case PPC::RLDCL_rec: in instrHasImmForm()
4032 case PPC::RLDCR: in instrHasImmForm()
4033 case PPC::RLDCR_rec: in instrHasImmForm()
4034 case PPC::SLD: in instrHasImmForm()
4035 case PPC::SLD_rec: in instrHasImmForm()
4036 case PPC::SRD: in instrHasImmForm()
4037 case PPC::SRD_rec: in instrHasImmForm()
4038 case PPC::SRAD: in instrHasImmForm()
4039 case PPC::SRAD_rec: in instrHasImmForm()
4049 if (Opc == PPC::RLDCL || Opc == PPC::RLDCL_rec || Opc == PPC::RLDCR || in instrHasImmForm()
4050 Opc == PPC::RLDCR_rec) in instrHasImmForm()
4056 case PPC::RLDCL: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
4057 case PPC::RLDCL_rec: in instrHasImmForm()
4058 III.ImmOpcode = PPC::RLDICL_rec; in instrHasImmForm()
4060 case PPC::RLDCR: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
4061 case PPC::RLDCR_rec: in instrHasImmForm()
4062 III.ImmOpcode = PPC::RLDICR_rec; in instrHasImmForm()
4064 case PPC::SLD: III.ImmOpcode = PPC::RLDICR; break; in instrHasImmForm()
4065 case PPC::SLD_rec: in instrHasImmForm()
4066 III.ImmOpcode = PPC::RLDICR_rec; in instrHasImmForm()
4068 case PPC::SRD: III.ImmOpcode = PPC::RLDICL; break; in instrHasImmForm()
4069 case PPC::SRD_rec: in instrHasImmForm()
4070 III.ImmOpcode = PPC::RLDICL_rec; in instrHasImmForm()
4072 case PPC::SRAD: in instrHasImmForm()
4075 III.ImmOpcode = PPC::SRADI; in instrHasImmForm()
4077 case PPC::SRAD_rec: in instrHasImmForm()
4080 III.ImmOpcode = PPC::SRADI_rec; in instrHasImmForm()
4085 case PPC::LBZX: in instrHasImmForm()
4086 case PPC::LBZX8: in instrHasImmForm()
4087 case PPC::LHZX: in instrHasImmForm()
4088 case PPC::LHZX8: in instrHasImmForm()
4089 case PPC::LHAX: in instrHasImmForm()
4090 case PPC::LHAX8: in instrHasImmForm()
4091 case PPC::LWZX: in instrHasImmForm()
4092 case PPC::LWZX8: in instrHasImmForm()
4093 case PPC::LWAX: in instrHasImmForm()
4094 case PPC::LDX: in instrHasImmForm()
4095 case PPC::LFSX: in instrHasImmForm()
4096 case PPC::LFDX: in instrHasImmForm()
4097 case PPC::STBX: in instrHasImmForm()
4098 case PPC::STBX8: in instrHasImmForm()
4099 case PPC::STHX: in instrHasImmForm()
4100 case PPC::STHX8: in instrHasImmForm()
4101 case PPC::STWX: in instrHasImmForm()
4102 case PPC::STWX8: in instrHasImmForm()
4103 case PPC::STDX: in instrHasImmForm()
4104 case PPC::STFSX: in instrHasImmForm()
4105 case PPC::STFDX: in instrHasImmForm()
4115 case PPC::LBZX: III.ImmOpcode = PPC::LBZ; break; in instrHasImmForm()
4116 case PPC::LBZX8: III.ImmOpcode = PPC::LBZ8; break; in instrHasImmForm()
4117 case PPC::LHZX: III.ImmOpcode = PPC::LHZ; break; in instrHasImmForm()
4118 case PPC::LHZX8: III.ImmOpcode = PPC::LHZ8; break; in instrHasImmForm()
4119 case PPC::LHAX: III.ImmOpcode = PPC::LHA; break; in instrHasImmForm()
4120 case PPC::LHAX8: III.ImmOpcode = PPC::LHA8; break; in instrHasImmForm()
4121 case PPC::LWZX: III.ImmOpcode = PPC::LWZ; break; in instrHasImmForm()
4122 case PPC::LWZX8: III.ImmOpcode = PPC::LWZ8; break; in instrHasImmForm()
4123 case PPC::LWAX: in instrHasImmForm()
4124 III.ImmOpcode = PPC::LWA; in instrHasImmForm()
4127 case PPC::LDX: III.ImmOpcode = PPC::LD; III.ImmMustBeMultipleOf = 4; break; in instrHasImmForm()
4128 case PPC::LFSX: III.ImmOpcode = PPC::LFS; break; in instrHasImmForm()
4129 case PPC::LFDX: III.ImmOpcode = PPC::LFD; break; in instrHasImmForm()
4130 case PPC::STBX: III.ImmOpcode = PPC::STB; break; in instrHasImmForm()
4131 case PPC::STBX8: III.ImmOpcode = PPC::STB8; break; in instrHasImmForm()
4132 case PPC::STHX: III.ImmOpcode = PPC::STH; break; in instrHasImmForm()
4133 case PPC::STHX8: III.ImmOpcode = PPC::STH8; break; in instrHasImmForm()
4134 case PPC::STWX: III.ImmOpcode = PPC::STW; break; in instrHasImmForm()
4135 case PPC::STWX8: III.ImmOpcode = PPC::STW8; break; in instrHasImmForm()
4136 case PPC::STDX: in instrHasImmForm()
4137 III.ImmOpcode = PPC::STD; in instrHasImmForm()
4140 case PPC::STFSX: III.ImmOpcode = PPC::STFS; break; in instrHasImmForm()
4141 case PPC::STFDX: III.ImmOpcode = PPC::STFD; break; in instrHasImmForm()
4144 case PPC::LBZUX: in instrHasImmForm()
4145 case PPC::LBZUX8: in instrHasImmForm()
4146 case PPC::LHZUX: in instrHasImmForm()
4147 case PPC::LHZUX8: in instrHasImmForm()
4148 case PPC::LHAUX: in instrHasImmForm()
4149 case PPC::LHAUX8: in instrHasImmForm()
4150 case PPC::LWZUX: in instrHasImmForm()
4151 case PPC::LWZUX8: in instrHasImmForm()
4152 case PPC::LDUX: in instrHasImmForm()
4153 case PPC::LFSUX: in instrHasImmForm()
4154 case PPC::LFDUX: in instrHasImmForm()
4155 case PPC::STBUX: in instrHasImmForm()
4156 case PPC::STBUX8: in instrHasImmForm()
4157 case PPC::STHUX: in instrHasImmForm()
4158 case PPC::STHUX8: in instrHasImmForm()
4159 case PPC::STWUX: in instrHasImmForm()
4160 case PPC::STWUX8: in instrHasImmForm()
4161 case PPC::STDUX: in instrHasImmForm()
4162 case PPC::STFSUX: in instrHasImmForm()
4163 case PPC::STFDUX: in instrHasImmForm()
4173 case PPC::LBZUX: III.ImmOpcode = PPC::LBZU; break; in instrHasImmForm()
4174 case PPC::LBZUX8: III.ImmOpcode = PPC::LBZU8; break; in instrHasImmForm()
4175 case PPC::LHZUX: III.ImmOpcode = PPC::LHZU; break; in instrHasImmForm()
4176 case PPC::LHZUX8: III.ImmOpcode = PPC::LHZU8; break; in instrHasImmForm()
4177 case PPC::LHAUX: III.ImmOpcode = PPC::LHAU; break; in instrHasImmForm()
4178 case PPC::LHAUX8: III.ImmOpcode = PPC::LHAU8; break; in instrHasImmForm()
4179 case PPC::LWZUX: III.ImmOpcode = PPC::LWZU; break; in instrHasImmForm()
4180 case PPC::LWZUX8: III.ImmOpcode = PPC::LWZU8; break; in instrHasImmForm()
4181 case PPC::LDUX: in instrHasImmForm()
4182 III.ImmOpcode = PPC::LDU; in instrHasImmForm()
4185 case PPC::LFSUX: III.ImmOpcode = PPC::LFSU; break; in instrHasImmForm()
4186 case PPC::LFDUX: III.ImmOpcode = PPC::LFDU; break; in instrHasImmForm()
4187 case PPC::STBUX: III.ImmOpcode = PPC::STBU; break; in instrHasImmForm()
4188 case PPC::STBUX8: III.ImmOpcode = PPC::STBU8; break; in instrHasImmForm()
4189 case PPC::STHUX: III.ImmOpcode = PPC::STHU; break; in instrHasImmForm()
4190 case PPC::STHUX8: III.ImmOpcode = PPC::STHU8; break; in instrHasImmForm()
4191 case PPC::STWUX: III.ImmOpcode = PPC::STWU; break; in instrHasImmForm()
4192 case PPC::STWUX8: III.ImmOpcode = PPC::STWU8; break; in instrHasImmForm()
4193 case PPC::STDUX: in instrHasImmForm()
4194 III.ImmOpcode = PPC::STDU; in instrHasImmForm()
4197 case PPC::STFSUX: III.ImmOpcode = PPC::STFSU; break; in instrHasImmForm()
4198 case PPC::STFDUX: III.ImmOpcode = PPC::STFDU; break; in instrHasImmForm()
4205 case PPC::LXVX: in instrHasImmForm()
4206 case PPC::LXSSPX: in instrHasImmForm()
4207 case PPC::LXSDX: in instrHasImmForm()
4208 case PPC::STXVX: in instrHasImmForm()
4209 case PPC::STXSSPX: in instrHasImmForm()
4210 case PPC::STXSDX: in instrHasImmForm()
4211 case PPC::XFLOADf32: in instrHasImmForm()
4212 case PPC::XFLOADf64: in instrHasImmForm()
4213 case PPC::XFSTOREf32: in instrHasImmForm()
4214 case PPC::XFSTOREf64: in instrHasImmForm()
4227 case PPC::LXVX: in instrHasImmForm()
4228 III.ImmOpcode = PPC::LXV; in instrHasImmForm()
4231 case PPC::LXSSPX: in instrHasImmForm()
4234 III.ImmOpcode = PPC::LXSSP; in instrHasImmForm()
4236 III.ImmOpcode = PPC::LFS; in instrHasImmForm()
4242 case PPC::XFLOADf32: in instrHasImmForm()
4243 III.ImmOpcode = PPC::DFLOADf32; in instrHasImmForm()
4245 case PPC::LXSDX: in instrHasImmForm()
4248 III.ImmOpcode = PPC::LXSD; in instrHasImmForm()
4250 III.ImmOpcode = PPC::LFD; in instrHasImmForm()
4256 case PPC::XFLOADf64: in instrHasImmForm()
4257 III.ImmOpcode = PPC::DFLOADf64; in instrHasImmForm()
4259 case PPC::STXVX: in instrHasImmForm()
4260 III.ImmOpcode = PPC::STXV; in instrHasImmForm()
4263 case PPC::STXSSPX: in instrHasImmForm()
4266 III.ImmOpcode = PPC::STXSSP; in instrHasImmForm()
4268 III.ImmOpcode = PPC::STFS; in instrHasImmForm()
4274 case PPC::XFSTOREf32: in instrHasImmForm()
4275 III.ImmOpcode = PPC::DFSTOREf32; in instrHasImmForm()
4277 case PPC::STXSDX: in instrHasImmForm()
4280 III.ImmOpcode = PPC::STXSD; in instrHasImmForm()
4282 III.ImmOpcode = PPC::STFD; in instrHasImmForm()
4288 case PPC::XFSTOREf64: in instrHasImmForm()
4289 III.ImmOpcode = PPC::DFSTOREf64; in instrHasImmForm()
4363 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO && in isUseMIElgibleForForwarding()
4364 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8) in isUseMIElgibleForForwarding()
4381 if (Opc != PPC::ADDItocL && Opc != PPC::ADDI && Opc != PPC::ADDI8) in isDefMIElgibleForForwarding()
4446 if (DefMI.getOpcode() == PPC::ADDItocL) { in isImmElgibleForForwarding()
4495 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in simplifyToLI()
4520 case PPC::CMPWI: in simplifyToLI()
4521 case PPC::CMPLWI: in simplifyToLI()
4522 case PPC::CMPDI: in simplifyToLI()
4523 case PPC::CMPLDI: { in simplifyToLI()
4541 if (UseOpc != PPC::ISEL && UseOpc != PPC::ISEL8) in simplifyToLI()
4548 if (RegToCopy == PPC::NoRegister) in simplifyToLI()
4551 if (RegToCopy == PPC::ZERO || RegToCopy == PPC::ZERO8) { in simplifyToLI()
4552 CompareUseMI.setDesc(get(UseOpc == PPC::ISEL8 ? PPC::LI8 : PPC::LI)); in simplifyToLI()
4563 CompareUseMI.setDesc(get(PPC::COPY)); in simplifyToLI()
4580 case PPC::ADDI: in simplifyToLI()
4581 case PPC::ADDI8: { in simplifyToLI()
4586 Is64BitLI = Opc == PPC::ADDI8; in simplifyToLI()
4592 case PPC::SUBFIC: in simplifyToLI()
4593 case PPC::SUBFIC8: { in simplifyToLI()
4600 Is64BitLI = Opc == PPC::SUBFIC8; in simplifyToLI()
4606 case PPC::RLDICL: in simplifyToLI()
4607 case PPC::RLDICL_rec: in simplifyToLI()
4608 case PPC::RLDICL_32: in simplifyToLI()
4609 case PPC::RLDICL_32_64: { in simplifyToLI()
4613 APInt InVal((Opc == PPC::RLDICL || Opc == PPC::RLDICL_rec) ? 64 : 32, in simplifyToLI()
4622 (Opc == PPC::RLDICL_rec && isUInt<16>(InVal.getSExtValue()))) { in simplifyToLI()
4624 Is64BitLI = Opc != PPC::RLDICL_32; in simplifyToLI()
4626 SetCR = Opc == PPC::RLDICL_rec; in simplifyToLI()
4631 case PPC::RLWINM: in simplifyToLI()
4632 case PPC::RLWINM8: in simplifyToLI()
4633 case PPC::RLWINM_rec: in simplifyToLI()
4634 case PPC::RLWINM8_rec: { in simplifyToLI()
4646 ValueFits |= ((Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec) && in simplifyToLI()
4650 Is64BitLI = Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec; in simplifyToLI()
4652 SetCR = Opc == PPC::RLWINM_rec || Opc == PPC::RLWINM8_rec; in simplifyToLI()
4657 case PPC::ORI: in simplifyToLI()
4658 case PPC::ORI8: in simplifyToLI()
4659 case PPC::XORI: in simplifyToLI()
4660 case PPC::XORI8: { in simplifyToLI()
4663 if (Opc == PPC::ORI || Opc == PPC::ORI8) in simplifyToLI()
4669 Is64BitLI = Opc == PPC::ORI8 || Opc == PPC::XORI8; in simplifyToLI()
4743 assert((XFormOpcode != PPC::INSTRUCTION_LIST_END) && in transformToNewImmFormFedByAdd()
4749 ? PPC::isVFRegister(MI.getOperand(0).getReg()) in transformToNewImmFormFedByAdd()
4860 if (DefMI.getOpcode() == PPC::ADDItocL) in transformToImmFormFedByAdd()
4898 if ((DefMI.getOpcode() != PPC::LI && DefMI.getOpcode() != PPC::LI8) || in transformToImmFormFedByLI()
4934 if ((NewZeroReg == PPC::R0 || NewZeroReg == PPC::X0) && in transformToImmFormFedByLI()
4937 if ((OrigZeroReg == PPC::R0 || OrigZeroReg == PPC::X0) && in transformToImmFormFedByLI()
4943 bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLW_rec || in transformToImmFormFedByLI()
4944 Opc == PPC::SRW || Opc == PPC::SRW_rec || in transformToImmFormFedByLI()
4945 Opc == PPC::SLW8 || Opc == PPC::SLW8_rec || in transformToImmFormFedByLI()
4946 Opc == PPC::SRW8 || Opc == PPC::SRW8_rec; in transformToImmFormFedByLI()
4947 bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLD_rec || in transformToImmFormFedByLI()
4948 Opc == PPC::SRD || Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
4949 bool SetCR = Opc == PPC::SLW_rec || Opc == PPC::SRW_rec || in transformToImmFormFedByLI()
4950 Opc == PPC::SLD_rec || Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
4951 bool RightShift = Opc == PPC::SRW || Opc == PPC::SRW_rec || Opc == PPC::SRD || in transformToImmFormFedByLI()
4952 Opc == PPC::SRD_rec; in transformToImmFormFedByLI()
4979 MI.setDesc(get(PPC::COPY)); in transformToImmFormFedByLI()
5028 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ? in transformToImmFormFedByLI()
5029 &PPC::GPRC_and_GPRC_NOR0RegClass : &PPC::G8RC_and_G8RC_NOX0RegClass; in transformToImmFormFedByLI()
5046 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) in updatedRC()
5047 return &PPC::VSRCRegClass; in updatedRC()
5052 return PPC::getRecordFormOpcode(Opcode); in getRecordFormOpcode()
5056 return (Opcode == PPC::LBZU || Opcode == PPC::LBZUX || Opcode == PPC::LBZU8 || in isOpZeroOfSubwordPreincLoad()
5057 Opcode == PPC::LBZUX8 || Opcode == PPC::LHZU || in isOpZeroOfSubwordPreincLoad()
5058 Opcode == PPC::LHZUX || Opcode == PPC::LHZU8 || in isOpZeroOfSubwordPreincLoad()
5059 Opcode == PPC::LHZUX8); in isOpZeroOfSubwordPreincLoad()
5084 if (Opcode == PPC::RLDICL && MI->getOperand(3).getImm() >= 33) in definedBySignExtendingOp()
5090 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in definedBySignExtendingOp()
5091 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec) && in definedBySignExtendingOp()
5098 if (Opcode == PPC::ANDIS_rec || Opcode == PPC::ANDIS8_rec) { in definedBySignExtendingOp()
5126 if ((isOpZeroOfSubwordPreincLoad(Opcode) || Opcode == PPC::LWZU || in definedByZeroExtendingOp()
5127 Opcode == PPC::LWZUX || Opcode == PPC::LWZU8 || Opcode == PPC::LWZUX8) && in definedByZeroExtendingOp()
5133 if (Opcode == PPC::LI || Opcode == PPC::LI8 || in definedByZeroExtendingOp()
5134 Opcode == PPC::LIS || Opcode == PPC::LIS8) { in definedByZeroExtendingOp()
5142 if ((Opcode == PPC::RLDICL || Opcode == PPC::RLDICL_rec || in definedByZeroExtendingOp()
5143 Opcode == PPC::RLDCL || Opcode == PPC::RLDCL_rec || in definedByZeroExtendingOp()
5144 Opcode == PPC::RLDICL_32_64) && in definedByZeroExtendingOp()
5148 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDIC_rec) && in definedByZeroExtendingOp()
5153 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINM_rec || in definedByZeroExtendingOp()
5154 Opcode == PPC::RLWNM || Opcode == PPC::RLWNM_rec || in definedByZeroExtendingOp()
5155 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in definedByZeroExtendingOp()
5170 Register SPReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in isTOCSaveMI()
5205 case PPC::COPY: { in isSignOrZeroExtended()
5232 if (SrcReg != PPC::X3) { in isSignOrZeroExtended()
5249 if (II == MBB->instr_begin() || (--II)->getOpcode() != PPC::ADJCALLSTACKUP) in isSignOrZeroExtended()
5273 case PPC::ORI: in isSignOrZeroExtended()
5274 case PPC::XORI: in isSignOrZeroExtended()
5275 case PPC::ORI8: in isSignOrZeroExtended()
5276 case PPC::XORI8: { in isSignOrZeroExtended()
5287 case PPC::ORIS: in isSignOrZeroExtended()
5288 case PPC::XORIS: in isSignOrZeroExtended()
5289 case PPC::ORIS8: in isSignOrZeroExtended()
5290 case PPC::XORIS8: { in isSignOrZeroExtended()
5303 case PPC::OR: in isSignOrZeroExtended()
5304 case PPC::OR8: in isSignOrZeroExtended()
5305 case PPC::ISEL: in isSignOrZeroExtended()
5306 case PPC::PHI: { in isSignOrZeroExtended()
5313 if (MI->getOpcode() == PPC::PHI) { in isSignOrZeroExtended()
5335 case PPC::AND: in isSignOrZeroExtended()
5336 case PPC::AND8: { in isSignOrZeroExtended()
5355 return (Opcode == (Subtarget.isPPC64() ? PPC::BDNZ8 : PPC::BDNZ)); in isBDNZ()
5373 if (LoopCount->getOpcode() == PPC::LI8 || LoopCount->getOpcode() == PPC::LI) in PPCPipelinerLoopInfo()
5392 MF->getSubtarget<PPCSubtarget>().isPPC64() ? PPC::CTR8 : PPC::CTR, in createTripCountGreaterCondition()
5408 if (LoopCount->getOpcode() == PPC::LI8 || in adjustTripCount()
5409 LoopCount->getOpcode() == PPC::LI) { in adjustTripCount()
5452 unsigned LOOPi = (Subtarget.isPPC64() ? PPC::MTCTR8loop : PPC::MTCTRloop); in findLoopInstr()