Lines Matching refs:isPPC64
169 bool isPPC64 = Subtarget.isPPC64(); in PPCTargetLowering() local
170 setMinStackArgumentAlignment(isPPC64 ? Align(8) : Align(4)); in PPCTargetLowering()
252 if (isPPC64 || Subtarget.hasFPCVT()) { in PPCTargetLowering()
255 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
258 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
262 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
265 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
269 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
272 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
276 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
279 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
470 (Subtarget.hasP9Vector() && Subtarget.isPPC64()) ? Custom : Expand); in PPCTargetLowering()
550 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
695 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64()) { in PPCTargetLowering()
997 if (Subtarget.hasDirectMove() && isPPC64) { in PPCTargetLowering()
1297 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand); in PPCTargetLowering()
1350 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
1352 if (!isPPC64) { in PPCTargetLowering()
1371 if (!isPPC64) { in PPCTargetLowering()
1382 else if (isPPC64) in PPCTargetLowering()
1387 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1); in PPCTargetLowering()
1435 setLibcallName(RTLIB::MEMCPY, isPPC64 ? "___memmove64" : "___memmove"); in PPCTargetLowering()
1436 setLibcallName(RTLIB::MEMMOVE, isPPC64 ? "___memmove64" : "___memmove"); in PPCTargetLowering()
1437 setLibcallName(RTLIB::MEMSET, isPPC64 ? "___memset64" : "___memset"); in PPCTargetLowering()
1438 setLibcallName(RTLIB::BZERO, isPPC64 ? "___bzero64" : "___bzero"); in PPCTargetLowering()
1629 Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in getByValTypeAlignment()
1649 if (!Subtarget.isPPC64() || !Subtarget.hasVSX()) in shallExtractConstSplatVectorElementToStore()
2862 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegImm()
2969 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectAddressRegRegOnly()
3173 const bool Is64Bit = Subtarget.isPPC64(); in getTOCEntry()
3237 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) in isJumpTableRelative()
3244 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBase()
3261 if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) in getPICJumpTableRelocBaseExpr()
3366 bool Is64Bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressAIX()
3448 bool is64bit = Subtarget.isPPC64(); in LowerGlobalTLSAddressLinux()
3697 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); in LowerVAARG()
3788 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only"); in LowerVACOPY()
3869 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE() local
3879 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl, in LowerINIT_TRAMPOLINE()
3880 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
3903 if (Subtarget.isPPC64() || Subtarget.isAIXABI()) { in LowerVASTART()
5108 bool isPPC64 = Subtarget.isPPC64(); in EmitTailCallStoreFPAndRetAddr() local
5109 int SlotSize = isPPC64 ? 8 : 4; in EmitTailCallStoreFPAndRetAddr()
5113 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
5124 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, in CalculateTailCallArgDest() argument
5130 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
5147 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5174 SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, in LowerMemOpCallTo() argument
5181 if (isPPC64) in LowerMemOpCallTo()
5191 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, in LowerMemOpCallTo()
5544 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5545 const Align Alignment = Subtarget.isPPC64() ? Align(8) : Align(4); in prepareDescriptorIndirectCall()
5594 const bool IsPPC64 = Subtarget.isPPC64(); in buildCallOperands()
5770 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) in isEligibleForTCO()
5850 if (Subtarget.isPPC64()) in LowerCall()
6735 const bool IsPPC64 = Subtarget.isPPC64(); in CC_AIX()
7076 const bool IsPPC64 = Subtarget.isPPC64(); in LowerFormalArguments_AIX()
7391 const bool IsPPC64 = Subtarget.isPPC64(); in LowerCall_AIX()
7655 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7786 bool isPPC64 = Subtarget.isPPC64(); in LowerSTACKRESTORE() local
7787 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1; in LowerSTACKRESTORE()
7807 bool isPPC64 = Subtarget.isPPC64(); in getReturnAddrFrameIndex() local
7820 RASI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, LROffset, false); in getReturnAddrFrameIndex()
7830 bool isPPC64 = Subtarget.isPPC64(); in getFramePointerFrameIndex() local
7843 FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); in getFramePointerFrameIndex()
7876 bool isPPC64 = Subtarget.isPPC64(); in LowerEH_DWARF_CFA() local
7879 int FI = MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, 0, false); in LowerEH_DWARF_CFA()
8220 DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in convertFPToInt()
8393 if (Subtarget.hasDirectMove() && Subtarget.isPPC64()) in LowerFP_TO_INT()
8684 Subtarget.isPPC64() && Subtarget.hasFPCVT()) in LowerINT_TO_FP()
8865 assert(Subtarget.isPPC64() && in LowerINT_TO_FP()
9457 if (Subtarget.hasVSX() && Subtarget.isPPC64() && in LowerBUILD_VECTOR()
10316 bool isPPC64 = Subtarget.isPPC64(); in LowerVPERM() local
10403 if (isPPC64 && (V1HasXXSWAPD || V2HasXXSWAPD)) { in LowerVPERM()
10736 if (Subtarget.isPPC64()) in LowerINTRINSIC_WO_CHAIN()
10993 unsigned Opcode = Subtarget.isPPC64() ? PPC::CFENCE8 : PPC::CFENCE; in LowerINTRINSIC_VOID()
10994 EVT FTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerINTRINSIC_VOID()
11010 if (!Subtarget.isPPC64()) in LowerBSWAP()
11196 if (Subtarget.isPPC64()) { in getDataClassTest()
11314 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
11748 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64()) in ReplaceNodeResults()
12047 bool is64bit = Subtarget.isPPC64(); in EmitPartwordAtomicBinary()
12314 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1; in emitEHSjLjSetJmp()
12316 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP; in emitEHSjLjSetJmp()
12319 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW)) in emitEHSjLjSetJmp()
12342 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg); in emitEHSjLjSetJmp()
12345 if (Subtarget.isPPC64()) { in emitEHSjLjSetJmp()
12505 const bool isPPC64 = Subtarget.isPPC64(); in emitProbedAlloca() local
12546 Register SPReg = isPPC64 ? PPC::X1 : PPC::R1; in emitProbedAlloca()
12547 Register FinalStackPtr = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12548 Register FramePointer = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12549 Register ActualNegSizeReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12557 isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64 : PPC::PREPARE_PROBED_ALLOCA_32; in emitProbedAlloca()
12563 ProbeOpc = isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_NEGSIZE_SAME_REG_64 in emitProbedAlloca()
12572 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), in emitProbedAlloca()
12580 Register ScratchReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12582 Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12583 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg) in emitProbedAlloca()
12585 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI), in emitProbedAlloca()
12590 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LI8 : PPC::LI), ScratchReg) in emitProbedAlloca()
12595 Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12596 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div) in emitProbedAlloca()
12599 Register Mul = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12600 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::MULLD : PPC::MULLW), Mul) in emitProbedAlloca()
12603 Register NegMod = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12604 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), NegMod) in emitProbedAlloca()
12607 BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) in emitProbedAlloca()
12616 BuildMI(TestMBB, DL, TII->get(isPPC64 ? PPC::CMPD : PPC::CMPW), CmpResult) in emitProbedAlloca()
12630 BuildMI(BlockMBB, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg) in emitProbedAlloca()
12641 MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC); in emitProbedAlloca()
12643 TII->get(isPPC64 ? PPC::DYNAREAOFFSET8 : PPC::DYNAREAOFFSET), in emitProbedAlloca()
12647 BuildMI(TailMBB, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), DstReg) in emitProbedAlloca()
13040 bool is64bit = Subtarget.isPPC64(); in EmitInstrWithCustomInserter()
14157 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
15163 (Op1VT == MVT::i32 || (Op1VT == MVT::i64 && Subtarget.isPPC64()) || in combineStoreFPToInt()
15666 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
15701 if (Subtarget.isPPC64() && !DCI.isBeforeLegalize() && in PerformDAGCombine()
16113 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
16364 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
16595 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16599 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16695 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
16875 bool isPPC64 = Subtarget.isPPC64(); in LowerRETURNADDR() local
16887 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
16909 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR() local
16915 FrameReg = isPPC64 ? PPC::X1 : PPC::R1; in LowerFRAMEADDR()
16917 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; in LowerFRAMEADDR()
16931 bool isPPC64 = Subtarget.isPPC64(); in getRegisterByName() local
16933 bool is64Bit = isPPC64 && VT == LLT::scalar(64); in getRegisterByName()
16939 .Case("r2", isPPC64 ? Register() : PPC::R2) in getRegisterByName()
17158 if (Subtarget.isPPC64()) { in getOptimalMemOpType()
17197 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
17381 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3; in getExceptionPointerRegister()
17386 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; in getExceptionSelectorRegister()
17589 if (!Subtarget.isISA3_0() || !Subtarget.isPPC64() || in combineSHL()
17633 if (!Subtarget.isPPC64()) in combineADDToADDZE()
18251 Disp = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectForceXFormMode()
18472 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18528 Disp = FI ? DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO, in SelectOptimalAddrMode()
18549 return Subtarget.isPPC64() && Subtarget.hasQuadwordAtomics(); in shouldInlineQuadwordAtomics()