Lines Matching refs:MVT
173 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
176 addRegisterClass(MVT::f32, &PPC::GPRCRegClass); in PPCTargetLowering()
179 addRegisterClass(MVT::f64, &PPC::SPERCRegClass); in PPCTargetLowering()
181 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
182 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
187 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in PPCTargetLowering()
188 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in PPCTargetLowering()
191 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); in PPCTargetLowering()
194 setOperationAction(ISD::INLINEASM, MVT::Other, Custom); in PPCTargetLowering()
195 setOperationAction(ISD::INLINEASM_BR, MVT::Other, Custom); in PPCTargetLowering()
198 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
199 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
200 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in PPCTargetLowering()
204 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
205 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
206 setTruncStoreAction(MVT::f64, MVT::f16, Legal); in PPCTargetLowering()
207 setTruncStoreAction(MVT::f32, MVT::f16, Legal); in PPCTargetLowering()
210 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); in PPCTargetLowering()
211 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand); in PPCTargetLowering()
212 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand); in PPCTargetLowering()
213 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); in PPCTargetLowering()
214 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand); in PPCTargetLowering()
215 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand); in PPCTargetLowering()
216 setTruncStoreAction(MVT::f64, MVT::f16, Expand); in PPCTargetLowering()
217 setTruncStoreAction(MVT::f32, MVT::f16, Expand); in PPCTargetLowering()
220 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
223 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
224 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
225 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
226 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
227 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
228 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
229 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
230 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
231 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
232 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
234 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
235 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
236 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
237 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
241 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; in PPCTargetLowering()
242 for (MVT VT : ScalarIntVTs) { in PPCTargetLowering()
250 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
253 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
254 AddPromotedToType(ISD::STRICT_SINT_TO_FP, MVT::i1, in PPCTargetLowering()
255 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
256 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
257 AddPromotedToType(ISD::STRICT_UINT_TO_FP, MVT::i1, in PPCTargetLowering()
258 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
260 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
261 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, in PPCTargetLowering()
262 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
263 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in PPCTargetLowering()
264 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
265 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
267 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i1, Promote); in PPCTargetLowering()
268 AddPromotedToType(ISD::STRICT_FP_TO_SINT, MVT::i1, in PPCTargetLowering()
269 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
270 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i1, Promote); in PPCTargetLowering()
271 AddPromotedToType(ISD::STRICT_FP_TO_UINT, MVT::i1, in PPCTargetLowering()
272 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
274 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in PPCTargetLowering()
275 AddPromotedToType(ISD::FP_TO_SINT, MVT::i1, in PPCTargetLowering()
276 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
277 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote); in PPCTargetLowering()
278 AddPromotedToType(ISD::FP_TO_UINT, MVT::i1, in PPCTargetLowering()
279 isPPC64 ? MVT::i64 : MVT::i32); in PPCTargetLowering()
281 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
282 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
283 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
284 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
288 setOperationAction(ISD::LOAD, MVT::i1, Custom); in PPCTargetLowering()
289 setOperationAction(ISD::STORE, MVT::i1, Custom); in PPCTargetLowering()
293 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom); in PPCTargetLowering()
295 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
296 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
297 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
298 setTruncStoreAction(VT, MVT::i1, Expand); in PPCTargetLowering()
301 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass); in PPCTargetLowering()
306 setOperationAction(ISD::FP_TO_SINT, MVT::ppcf128, Custom); in PPCTargetLowering()
307 setOperationAction(ISD::FP_TO_UINT, MVT::ppcf128, Custom); in PPCTargetLowering()
308 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::ppcf128, Custom); in PPCTargetLowering()
309 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::ppcf128, Custom); in PPCTargetLowering()
312 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); in PPCTargetLowering()
313 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); in PPCTargetLowering()
314 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); in PPCTargetLowering()
315 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); in PPCTargetLowering()
316 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); in PPCTargetLowering()
317 setOperationAction(ISD::FREM, MVT::ppcf128, Expand); in PPCTargetLowering()
327 setOperationAction(ISD::SREM, MVT::i32, Legal); in PPCTargetLowering()
328 setOperationAction(ISD::UREM, MVT::i32, Legal); in PPCTargetLowering()
329 setOperationAction(ISD::SREM, MVT::i64, Legal); in PPCTargetLowering()
330 setOperationAction(ISD::UREM, MVT::i64, Legal); in PPCTargetLowering()
332 setOperationAction(ISD::SREM, MVT::i32, Expand); in PPCTargetLowering()
333 setOperationAction(ISD::UREM, MVT::i32, Expand); in PPCTargetLowering()
334 setOperationAction(ISD::SREM, MVT::i64, Expand); in PPCTargetLowering()
335 setOperationAction(ISD::UREM, MVT::i64, Expand); in PPCTargetLowering()
339 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
340 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); in PPCTargetLowering()
341 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
342 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); in PPCTargetLowering()
343 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); in PPCTargetLowering()
344 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); in PPCTargetLowering()
345 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); in PPCTargetLowering()
346 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); in PPCTargetLowering()
350 setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal); in PPCTargetLowering()
351 setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal); in PPCTargetLowering()
352 setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal); in PPCTargetLowering()
353 setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal); in PPCTargetLowering()
354 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
356 setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal); in PPCTargetLowering()
357 setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal); in PPCTargetLowering()
358 setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal); in PPCTargetLowering()
359 setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal); in PPCTargetLowering()
362 setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal); in PPCTargetLowering()
363 setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal); in PPCTargetLowering()
367 setOperationAction(ISD::STRICT_FRINT, MVT::f32, Legal); in PPCTargetLowering()
368 setOperationAction(ISD::STRICT_FRINT, MVT::f64, Legal); in PPCTargetLowering()
372 setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal); in PPCTargetLowering()
373 setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal); in PPCTargetLowering()
377 setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
378 setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal); in PPCTargetLowering()
379 setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
380 setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal); in PPCTargetLowering()
382 setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
383 setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal); in PPCTargetLowering()
384 setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
385 setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal); in PPCTargetLowering()
389 setOperationAction(ISD::FSIN , MVT::f64, Expand); in PPCTargetLowering()
390 setOperationAction(ISD::FCOS , MVT::f64, Expand); in PPCTargetLowering()
391 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); in PPCTargetLowering()
392 setOperationAction(ISD::FREM , MVT::f64, Expand); in PPCTargetLowering()
393 setOperationAction(ISD::FPOW , MVT::f64, Expand); in PPCTargetLowering()
394 setOperationAction(ISD::FSIN , MVT::f32, Expand); in PPCTargetLowering()
395 setOperationAction(ISD::FCOS , MVT::f32, Expand); in PPCTargetLowering()
396 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); in PPCTargetLowering()
397 setOperationAction(ISD::FREM , MVT::f32, Expand); in PPCTargetLowering()
398 setOperationAction(ISD::FPOW , MVT::f32, Expand); in PPCTargetLowering()
403 setOperationAction(ISD::FSIN , MVT::f64, Custom); in PPCTargetLowering()
404 setOperationAction(ISD::FCOS , MVT::f64, Custom); in PPCTargetLowering()
405 setOperationAction(ISD::FPOW , MVT::f64, Custom); in PPCTargetLowering()
406 setOperationAction(ISD::FLOG, MVT::f64, Custom); in PPCTargetLowering()
407 setOperationAction(ISD::FLOG10, MVT::f64, Custom); in PPCTargetLowering()
408 setOperationAction(ISD::FEXP, MVT::f64, Custom); in PPCTargetLowering()
409 setOperationAction(ISD::FSIN , MVT::f32, Custom); in PPCTargetLowering()
410 setOperationAction(ISD::FCOS , MVT::f32, Custom); in PPCTargetLowering()
411 setOperationAction(ISD::FPOW , MVT::f32, Custom); in PPCTargetLowering()
412 setOperationAction(ISD::FLOG, MVT::f32, Custom); in PPCTargetLowering()
413 setOperationAction(ISD::FLOG10, MVT::f32, Custom); in PPCTargetLowering()
414 setOperationAction(ISD::FEXP, MVT::f32, Custom); in PPCTargetLowering()
418 setOperationAction(ISD::FMA , MVT::f64, Expand); in PPCTargetLowering()
419 setOperationAction(ISD::FMA , MVT::f32, Expand); in PPCTargetLowering()
421 setOperationAction(ISD::FMA , MVT::f64, Legal); in PPCTargetLowering()
422 setOperationAction(ISD::FMA , MVT::f32, Legal); in PPCTargetLowering()
426 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
428 setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom); in PPCTargetLowering()
434 setOperationAction(ISD::FSQRT, MVT::f64, Expand); in PPCTargetLowering()
439 setOperationAction(ISD::FSQRT, MVT::f32, Expand); in PPCTargetLowering()
442 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal); in PPCTargetLowering()
443 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal); in PPCTargetLowering()
445 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); in PPCTargetLowering()
446 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); in PPCTargetLowering()
450 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); in PPCTargetLowering()
451 setOperationAction(ISD::FCEIL, MVT::f64, Legal); in PPCTargetLowering()
452 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); in PPCTargetLowering()
453 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
455 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in PPCTargetLowering()
456 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in PPCTargetLowering()
457 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); in PPCTargetLowering()
458 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
464 setOperationAction(ISD::BSWAP, MVT::i32, Legal); in PPCTargetLowering()
465 setOperationAction(ISD::BSWAP, MVT::i64, Legal); in PPCTargetLowering()
467 setOperationAction(ISD::BSWAP, MVT::i32, Expand); in PPCTargetLowering()
469 ISD::BSWAP, MVT::i64, in PPCTargetLowering()
475 setOperationAction(ISD::CTTZ , MVT::i32 , Legal); in PPCTargetLowering()
476 setOperationAction(ISD::CTTZ , MVT::i64 , Legal); in PPCTargetLowering()
478 setOperationAction(ISD::CTTZ , MVT::i32 , Expand); in PPCTargetLowering()
479 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in PPCTargetLowering()
483 setOperationAction(ISD::CTPOP, MVT::i32 , Legal); in PPCTargetLowering()
484 setOperationAction(ISD::CTPOP, MVT::i64 , Legal); in PPCTargetLowering()
486 setOperationAction(ISD::CTPOP, MVT::i32 , Expand); in PPCTargetLowering()
487 setOperationAction(ISD::CTPOP, MVT::i64 , Expand); in PPCTargetLowering()
491 setOperationAction(ISD::ROTR, MVT::i32 , Expand); in PPCTargetLowering()
492 setOperationAction(ISD::ROTR, MVT::i64 , Expand); in PPCTargetLowering()
496 setOperationAction(ISD::SELECT, MVT::i32, Expand); in PPCTargetLowering()
497 setOperationAction(ISD::SELECT, MVT::i64, Expand); in PPCTargetLowering()
498 setOperationAction(ISD::SELECT, MVT::f32, Expand); in PPCTargetLowering()
499 setOperationAction(ISD::SELECT, MVT::f64, Expand); in PPCTargetLowering()
503 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); in PPCTargetLowering()
504 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); in PPCTargetLowering()
508 setOperationAction(ISD::SETCC, MVT::i32, Custom); in PPCTargetLowering()
511 setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Legal); in PPCTargetLowering()
512 setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Legal); in PPCTargetLowering()
513 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Legal); in PPCTargetLowering()
515 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
516 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
517 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Legal); in PPCTargetLowering()
522 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in PPCTargetLowering()
524 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in PPCTargetLowering()
528 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
529 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
530 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
531 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in PPCTargetLowering()
532 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
533 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
536 setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal); in PPCTargetLowering()
537 setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal); in PPCTargetLowering()
540 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
541 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
544 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
545 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
546 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
547 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
551 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in PPCTargetLowering()
552 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in PPCTargetLowering()
553 setOperationAction(ISD::BITCAST, MVT::i64, Legal); in PPCTargetLowering()
554 setOperationAction(ISD::BITCAST, MVT::f64, Legal); in PPCTargetLowering()
556 setOperationAction(ISD::LRINT, MVT::f64, Legal); in PPCTargetLowering()
557 setOperationAction(ISD::LRINT, MVT::f32, Legal); in PPCTargetLowering()
558 setOperationAction(ISD::LLRINT, MVT::f64, Legal); in PPCTargetLowering()
559 setOperationAction(ISD::LLRINT, MVT::f32, Legal); in PPCTargetLowering()
560 setOperationAction(ISD::LROUND, MVT::f64, Legal); in PPCTargetLowering()
561 setOperationAction(ISD::LROUND, MVT::f32, Legal); in PPCTargetLowering()
562 setOperationAction(ISD::LLROUND, MVT::f64, Legal); in PPCTargetLowering()
563 setOperationAction(ISD::LLROUND, MVT::f32, Legal); in PPCTargetLowering()
566 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in PPCTargetLowering()
567 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in PPCTargetLowering()
568 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in PPCTargetLowering()
569 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in PPCTargetLowering()
573 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); in PPCTargetLowering()
581 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); in PPCTargetLowering()
582 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); in PPCTargetLowering()
586 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); in PPCTargetLowering()
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); in PPCTargetLowering()
588 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); in PPCTargetLowering()
589 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); in PPCTargetLowering()
590 setOperationAction(ISD::JumpTable, MVT::i32, Custom); in PPCTargetLowering()
591 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in PPCTargetLowering()
592 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in PPCTargetLowering()
593 setOperationAction(ISD::BlockAddress, MVT::i64, Custom); in PPCTargetLowering()
594 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); in PPCTargetLowering()
595 setOperationAction(ISD::JumpTable, MVT::i64, Custom); in PPCTargetLowering()
598 setOperationAction(ISD::TRAP, MVT::Other, Legal); in PPCTargetLowering()
601 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
602 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); in PPCTargetLowering()
605 setOperationAction(ISD::VASTART , MVT::Other, Custom); in PPCTargetLowering()
609 setOperationAction(ISD::VAARG, MVT::i1, Promote); in PPCTargetLowering()
610 AddPromotedToType(ISD::VAARG, MVT::i1, MVT::i64); in PPCTargetLowering()
611 setOperationAction(ISD::VAARG, MVT::i8, Promote); in PPCTargetLowering()
612 AddPromotedToType(ISD::VAARG, MVT::i8, MVT::i64); in PPCTargetLowering()
613 setOperationAction(ISD::VAARG, MVT::i16, Promote); in PPCTargetLowering()
614 AddPromotedToType(ISD::VAARG, MVT::i16, MVT::i64); in PPCTargetLowering()
615 setOperationAction(ISD::VAARG, MVT::i32, Promote); in PPCTargetLowering()
616 AddPromotedToType(ISD::VAARG, MVT::i32, MVT::i64); in PPCTargetLowering()
617 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
620 setOperationAction(ISD::VAARG, MVT::Other, Custom); in PPCTargetLowering()
621 setOperationAction(ISD::VAARG, MVT::i64, Custom); in PPCTargetLowering()
623 setOperationAction(ISD::VAARG, MVT::Other, Expand); in PPCTargetLowering()
627 setOperationAction(ISD::VACOPY , MVT::Other, Custom); in PPCTargetLowering()
629 setOperationAction(ISD::VACOPY , MVT::Other, Expand); in PPCTargetLowering()
632 setOperationAction(ISD::VAEND , MVT::Other, Expand); in PPCTargetLowering()
633 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); in PPCTargetLowering()
634 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); in PPCTargetLowering()
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); in PPCTargetLowering()
636 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); in PPCTargetLowering()
637 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom); in PPCTargetLowering()
638 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom); in PPCTargetLowering()
639 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); in PPCTargetLowering()
640 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom); in PPCTargetLowering()
643 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in PPCTargetLowering()
644 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f64, Custom); in PPCTargetLowering()
645 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::ppcf128, Custom); in PPCTargetLowering()
646 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom); in PPCTargetLowering()
647 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v2f64, Custom); in PPCTargetLowering()
650 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom); in PPCTargetLowering()
652 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom); in PPCTargetLowering()
653 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom); in PPCTargetLowering()
654 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom); in PPCTargetLowering()
655 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in PPCTargetLowering()
659 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in PPCTargetLowering()
660 setCondCodeAction(ISD::SETO, MVT::f64, Expand); in PPCTargetLowering()
661 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in PPCTargetLowering()
662 setCondCodeAction(ISD::SETUO, MVT::f64, Expand); in PPCTargetLowering()
664 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in PPCTargetLowering()
665 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); in PPCTargetLowering()
666 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in PPCTargetLowering()
667 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); in PPCTargetLowering()
668 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in PPCTargetLowering()
669 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); in PPCTargetLowering()
670 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); in PPCTargetLowering()
671 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); in PPCTargetLowering()
672 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in PPCTargetLowering()
673 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); in PPCTargetLowering()
674 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in PPCTargetLowering()
675 setCondCodeAction(ISD::SETONE, MVT::f64, Expand); in PPCTargetLowering()
677 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal); in PPCTargetLowering()
678 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal); in PPCTargetLowering()
682 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
683 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
684 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
685 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
686 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
687 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); in PPCTargetLowering()
688 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
689 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in PPCTargetLowering()
692 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
693 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
696 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
697 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
702 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Legal); in PPCTargetLowering()
703 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal); in PPCTargetLowering()
705 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Expand); in PPCTargetLowering()
706 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); in PPCTargetLowering()
713 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
714 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i64, Custom); in PPCTargetLowering()
715 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
716 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
717 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
718 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); in PPCTargetLowering()
719 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
720 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in PPCTargetLowering()
723 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
724 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
725 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
726 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
727 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
728 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); in PPCTargetLowering()
729 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
730 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in PPCTargetLowering()
735 addRegisterClass(MVT::i64, &PPC::G8RCRegClass); in PPCTargetLowering()
737 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
739 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
740 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); in PPCTargetLowering()
741 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); in PPCTargetLowering()
744 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
745 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); in PPCTargetLowering()
746 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); in PPCTargetLowering()
752 setOperationAction(ISD::FSHL, MVT::i64, Custom); in PPCTargetLowering()
753 setOperationAction(ISD::FSHR, MVT::i64, Custom); in PPCTargetLowering()
755 setOperationAction(ISD::FSHL, MVT::i32, Custom); in PPCTargetLowering()
756 setOperationAction(ISD::FSHR, MVT::i32, Custom); in PPCTargetLowering()
759 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f64, Legal); in PPCTargetLowering()
760 setOperationAction(ISD::FMAXNUM_IEEE, MVT::f32, Legal); in PPCTargetLowering()
761 setOperationAction(ISD::FMINNUM_IEEE, MVT::f64, Legal); in PPCTargetLowering()
762 setOperationAction(ISD::FMINNUM_IEEE, MVT::f32, Legal); in PPCTargetLowering()
766 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { in PPCTargetLowering()
774 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in PPCTargetLowering()
800 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { in PPCTargetLowering()
810 if (Subtarget.hasP9Altivec() && (VT.SimpleTy != MVT::v1i128)) in PPCTargetLowering()
817 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
821 AddPromotedToType (ISD::AND , VT, MVT::v4i32); in PPCTargetLowering()
823 AddPromotedToType (ISD::OR , VT, MVT::v4i32); in PPCTargetLowering()
825 AddPromotedToType (ISD::XOR , VT, MVT::v4i32); in PPCTargetLowering()
827 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); in PPCTargetLowering()
829 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); in PPCTargetLowering()
832 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); in PPCTargetLowering()
834 AddPromotedToType (ISD::STORE, VT, MVT::v4i32); in PPCTargetLowering()
876 for (MVT InnerVT : MVT::fixedlen_vector_valuetypes()) { in PPCTargetLowering()
883 setOperationAction(ISD::SELECT_CC, MVT::v4i32, Expand); in PPCTargetLowering()
885 setOperationAction(ISD::SMAX, MVT::v2i64, Expand); in PPCTargetLowering()
886 setOperationAction(ISD::SMIN, MVT::v2i64, Expand); in PPCTargetLowering()
887 setOperationAction(ISD::UMAX, MVT::v2i64, Expand); in PPCTargetLowering()
888 setOperationAction(ISD::UMIN, MVT::v2i64, Expand); in PPCTargetLowering()
893 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
897 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom); in PPCTargetLowering()
898 setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom); in PPCTargetLowering()
899 setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom); in PPCTargetLowering()
900 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom); in PPCTargetLowering()
901 setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom); in PPCTargetLowering()
903 setOperationAction(ISD::AND , MVT::v4i32, Legal); in PPCTargetLowering()
904 setOperationAction(ISD::OR , MVT::v4i32, Legal); in PPCTargetLowering()
905 setOperationAction(ISD::XOR , MVT::v4i32, Legal); in PPCTargetLowering()
906 setOperationAction(ISD::LOAD , MVT::v4i32, Legal); in PPCTargetLowering()
907 setOperationAction(ISD::SELECT, MVT::v4i32, in PPCTargetLowering()
909 setOperationAction(ISD::STORE , MVT::v4i32, Legal); in PPCTargetLowering()
910 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
911 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
912 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
913 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
914 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
915 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal); in PPCTargetLowering()
916 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
917 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in PPCTargetLowering()
918 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
919 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
920 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
921 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
924 setOperationAction(ISD::ROTL, MVT::v1i128, Custom); in PPCTargetLowering()
927 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8}) in PPCTargetLowering()
931 setOperationAction(ISD::ROTL, MVT::v2i64, Legal); in PPCTargetLowering()
933 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass); in PPCTargetLowering()
934 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass); in PPCTargetLowering()
935 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass); in PPCTargetLowering()
936 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass); in PPCTargetLowering()
938 setOperationAction(ISD::MUL, MVT::v4f32, Legal); in PPCTargetLowering()
939 setOperationAction(ISD::FMA, MVT::v4f32, Legal); in PPCTargetLowering()
942 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
943 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
944 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); in PPCTargetLowering()
948 setOperationAction(ISD::MUL, MVT::v4i32, Legal); in PPCTargetLowering()
950 setOperationAction(ISD::MUL, MVT::v4i32, Custom); in PPCTargetLowering()
953 setOperationAction(ISD::MUL, MVT::v2i64, Legal); in PPCTargetLowering()
954 setOperationAction(ISD::MULHS, MVT::v2i64, Legal); in PPCTargetLowering()
955 setOperationAction(ISD::MULHU, MVT::v2i64, Legal); in PPCTargetLowering()
956 setOperationAction(ISD::MULHS, MVT::v4i32, Legal); in PPCTargetLowering()
957 setOperationAction(ISD::MULHU, MVT::v4i32, Legal); in PPCTargetLowering()
958 setOperationAction(ISD::UDIV, MVT::v2i64, Legal); in PPCTargetLowering()
959 setOperationAction(ISD::SDIV, MVT::v2i64, Legal); in PPCTargetLowering()
960 setOperationAction(ISD::UDIV, MVT::v4i32, Legal); in PPCTargetLowering()
961 setOperationAction(ISD::SDIV, MVT::v4i32, Legal); in PPCTargetLowering()
962 setOperationAction(ISD::UREM, MVT::v2i64, Legal); in PPCTargetLowering()
963 setOperationAction(ISD::SREM, MVT::v2i64, Legal); in PPCTargetLowering()
964 setOperationAction(ISD::UREM, MVT::v4i32, Legal); in PPCTargetLowering()
965 setOperationAction(ISD::SREM, MVT::v4i32, Legal); in PPCTargetLowering()
966 setOperationAction(ISD::UREM, MVT::v1i128, Legal); in PPCTargetLowering()
967 setOperationAction(ISD::SREM, MVT::v1i128, Legal); in PPCTargetLowering()
968 setOperationAction(ISD::UDIV, MVT::v1i128, Legal); in PPCTargetLowering()
969 setOperationAction(ISD::SDIV, MVT::v1i128, Legal); in PPCTargetLowering()
970 setOperationAction(ISD::ROTL, MVT::v1i128, Legal); in PPCTargetLowering()
973 setOperationAction(ISD::MUL, MVT::v8i16, Legal); in PPCTargetLowering()
974 setOperationAction(ISD::MUL, MVT::v16i8, Custom); in PPCTargetLowering()
976 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
977 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
979 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); in PPCTargetLowering()
980 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); in PPCTargetLowering()
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); in PPCTargetLowering()
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in PPCTargetLowering()
985 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); in PPCTargetLowering()
986 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); in PPCTargetLowering()
987 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); in PPCTargetLowering()
988 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); in PPCTargetLowering()
991 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal); in PPCTargetLowering()
992 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal); in PPCTargetLowering()
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal); in PPCTargetLowering()
998 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal); in PPCTargetLowering()
999 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal); in PPCTargetLowering()
1000 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal); in PPCTargetLowering()
1001 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal); in PPCTargetLowering()
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
1007 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal); in PPCTargetLowering()
1012 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); in PPCTargetLowering()
1013 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); in PPCTargetLowering()
1016 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
1017 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
1018 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
1019 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal); in PPCTargetLowering()
1020 setOperationAction(ISD::FRINT, MVT::v2f64, Legal); in PPCTargetLowering()
1021 setOperationAction(ISD::FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
1022 setOperationAction(ISD::FROUND, MVT::f64, Legal); in PPCTargetLowering()
1023 setOperationAction(ISD::FRINT, MVT::f64, Legal); in PPCTargetLowering()
1025 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal); in PPCTargetLowering()
1026 setOperationAction(ISD::FRINT, MVT::v4f32, Legal); in PPCTargetLowering()
1027 setOperationAction(ISD::FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
1028 setOperationAction(ISD::FROUND, MVT::f32, Legal); in PPCTargetLowering()
1029 setOperationAction(ISD::FRINT, MVT::f32, Legal); in PPCTargetLowering()
1031 setOperationAction(ISD::MUL, MVT::v2f64, Legal); in PPCTargetLowering()
1032 setOperationAction(ISD::FMA, MVT::v2f64, Legal); in PPCTargetLowering()
1034 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
1035 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1038 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand); in PPCTargetLowering()
1039 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); in PPCTargetLowering()
1040 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); in PPCTargetLowering()
1041 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand); in PPCTargetLowering()
1043 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); in PPCTargetLowering()
1044 setOperationAction(ISD::STORE, MVT::v2f64, Legal); in PPCTargetLowering()
1046 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); in PPCTargetLowering()
1049 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass); in PPCTargetLowering()
1051 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass); in PPCTargetLowering()
1053 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass); in PPCTargetLowering()
1054 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass); in PPCTargetLowering()
1055 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass); in PPCTargetLowering()
1058 setOperationAction(ISD::SHL, MVT::v2i64, Legal); in PPCTargetLowering()
1059 setOperationAction(ISD::SRA, MVT::v2i64, Legal); in PPCTargetLowering()
1060 setOperationAction(ISD::SRL, MVT::v2i64, Legal); in PPCTargetLowering()
1066 setOperationAction(ISD::SHL, MVT::v1i128, Expand); in PPCTargetLowering()
1067 setOperationAction(ISD::SRL, MVT::v1i128, Expand); in PPCTargetLowering()
1068 setOperationAction(ISD::SRA, MVT::v1i128, Expand); in PPCTargetLowering()
1070 setOperationAction(ISD::SETCC, MVT::v2i64, Legal); in PPCTargetLowering()
1073 setOperationAction(ISD::SHL, MVT::v2i64, Expand); in PPCTargetLowering()
1074 setOperationAction(ISD::SRA, MVT::v2i64, Expand); in PPCTargetLowering()
1075 setOperationAction(ISD::SRL, MVT::v2i64, Expand); in PPCTargetLowering()
1077 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); in PPCTargetLowering()
1080 setOperationAction(ISD::ADD, MVT::v2i64, Expand); in PPCTargetLowering()
1081 setOperationAction(ISD::SUB, MVT::v2i64, Expand); in PPCTargetLowering()
1085 setOperationAction(ISD::SETCC, MVT::v1i128, Legal); in PPCTargetLowering()
1087 setOperationAction(ISD::SETCC, MVT::v1i128, Expand); in PPCTargetLowering()
1089 setOperationAction(ISD::LOAD, MVT::v2i64, Promote); in PPCTargetLowering()
1090 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
1091 setOperationAction(ISD::STORE, MVT::v2i64, Promote); in PPCTargetLowering()
1092 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64); in PPCTargetLowering()
1094 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); in PPCTargetLowering()
1096 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
1097 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
1098 setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
1099 setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v2i64, Legal); in PPCTargetLowering()
1100 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in PPCTargetLowering()
1102 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
1103 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal); in PPCTargetLowering()
1108 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
1109 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
1110 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
1111 setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
1112 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
1113 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
1114 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
1115 setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
1116 setOperationAction(ISD::UINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
1117 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
1118 setOperationAction(ISD::UINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
1119 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
1120 setOperationAction(ISD::SINT_TO_FP, MVT::v2i8, Custom); in PPCTargetLowering()
1121 setOperationAction(ISD::SINT_TO_FP, MVT::v4i8, Custom); in PPCTargetLowering()
1122 setOperationAction(ISD::SINT_TO_FP, MVT::v2i16, Custom); in PPCTargetLowering()
1123 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
1125 setOperationAction(ISD::FNEG, MVT::v4f32, Legal); in PPCTargetLowering()
1126 setOperationAction(ISD::FNEG, MVT::v2f64, Legal); in PPCTargetLowering()
1127 setOperationAction(ISD::FABS, MVT::v4f32, Legal); in PPCTargetLowering()
1128 setOperationAction(ISD::FABS, MVT::v2f64, Legal); in PPCTargetLowering()
1129 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal); in PPCTargetLowering()
1130 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Legal); in PPCTargetLowering()
1132 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); in PPCTargetLowering()
1133 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); in PPCTargetLowering()
1138 setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal); in PPCTargetLowering()
1139 setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal); in PPCTargetLowering()
1140 setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal); in PPCTargetLowering()
1141 setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal); in PPCTargetLowering()
1142 setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal); in PPCTargetLowering()
1143 setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal); in PPCTargetLowering()
1144 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal); in PPCTargetLowering()
1145 setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal); in PPCTargetLowering()
1146 setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal); in PPCTargetLowering()
1147 setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal); in PPCTargetLowering()
1148 setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal); in PPCTargetLowering()
1149 setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal); in PPCTargetLowering()
1150 setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal); in PPCTargetLowering()
1152 setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal); in PPCTargetLowering()
1153 setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal); in PPCTargetLowering()
1154 setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal); in PPCTargetLowering()
1155 setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal); in PPCTargetLowering()
1156 setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal); in PPCTargetLowering()
1157 setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal); in PPCTargetLowering()
1158 setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal); in PPCTargetLowering()
1159 setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal); in PPCTargetLowering()
1160 setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal); in PPCTargetLowering()
1161 setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal); in PPCTargetLowering()
1162 setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal); in PPCTargetLowering()
1163 setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal); in PPCTargetLowering()
1164 setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal); in PPCTargetLowering()
1166 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass); in PPCTargetLowering()
1167 addRegisterClass(MVT::f128, &PPC::VRRCRegClass); in PPCTargetLowering()
1169 for (MVT FPT : MVT::fp_valuetypes()) in PPCTargetLowering()
1170 setLoadExtAction(ISD::EXTLOAD, MVT::f128, FPT, Expand); in PPCTargetLowering()
1173 setOperationAction(ISD::SELECT, MVT::f128, Expand); in PPCTargetLowering()
1175 setTruncStoreAction(MVT::f128, MVT::f64, Expand); in PPCTargetLowering()
1176 setTruncStoreAction(MVT::f128, MVT::f32, Expand); in PPCTargetLowering()
1179 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); in PPCTargetLowering()
1180 setOperationAction(ISD::FSIN, MVT::f128, Expand); in PPCTargetLowering()
1181 setOperationAction(ISD::FCOS, MVT::f128, Expand); in PPCTargetLowering()
1182 setOperationAction(ISD::FPOW, MVT::f128, Expand); in PPCTargetLowering()
1183 setOperationAction(ISD::FPOWI, MVT::f128, Expand); in PPCTargetLowering()
1184 setOperationAction(ISD::FREM, MVT::f128, Expand); in PPCTargetLowering()
1188 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass); in PPCTargetLowering()
1189 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass); in PPCTargetLowering()
1193 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); in PPCTargetLowering()
1194 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); in PPCTargetLowering()
1198 setOperationAction(ISD::IS_FPCLASS, MVT::f32, Custom); in PPCTargetLowering()
1199 setOperationAction(ISD::IS_FPCLASS, MVT::f64, Custom); in PPCTargetLowering()
1200 setOperationAction(ISD::IS_FPCLASS, MVT::f128, Custom); in PPCTargetLowering()
1206 setOperationAction(ISD::SHL, MVT::v1i128, Legal); in PPCTargetLowering()
1207 setOperationAction(ISD::SRL, MVT::v1i128, Legal); in PPCTargetLowering()
1208 setOperationAction(ISD::SRA, MVT::v1i128, Expand); in PPCTargetLowering()
1210 setOperationAction(ISD::FADD, MVT::f128, Legal); in PPCTargetLowering()
1211 setOperationAction(ISD::FSUB, MVT::f128, Legal); in PPCTargetLowering()
1212 setOperationAction(ISD::FDIV, MVT::f128, Legal); in PPCTargetLowering()
1213 setOperationAction(ISD::FMUL, MVT::f128, Legal); in PPCTargetLowering()
1214 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); in PPCTargetLowering()
1216 setOperationAction(ISD::FMA, MVT::f128, Legal); in PPCTargetLowering()
1217 setCondCodeAction(ISD::SETULT, MVT::f128, Expand); in PPCTargetLowering()
1218 setCondCodeAction(ISD::SETUGT, MVT::f128, Expand); in PPCTargetLowering()
1219 setCondCodeAction(ISD::SETUEQ, MVT::f128, Expand); in PPCTargetLowering()
1220 setCondCodeAction(ISD::SETOGE, MVT::f128, Expand); in PPCTargetLowering()
1221 setCondCodeAction(ISD::SETOLE, MVT::f128, Expand); in PPCTargetLowering()
1222 setCondCodeAction(ISD::SETONE, MVT::f128, Expand); in PPCTargetLowering()
1224 setOperationAction(ISD::FTRUNC, MVT::f128, Legal); in PPCTargetLowering()
1225 setOperationAction(ISD::FRINT, MVT::f128, Legal); in PPCTargetLowering()
1226 setOperationAction(ISD::FFLOOR, MVT::f128, Legal); in PPCTargetLowering()
1227 setOperationAction(ISD::FCEIL, MVT::f128, Legal); in PPCTargetLowering()
1228 setOperationAction(ISD::FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
1229 setOperationAction(ISD::FROUND, MVT::f128, Legal); in PPCTargetLowering()
1231 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1232 setOperationAction(ISD::FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1233 setOperationAction(ISD::BITCAST, MVT::i128, Custom); in PPCTargetLowering()
1236 setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal); in PPCTargetLowering()
1237 setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal); in PPCTargetLowering()
1238 setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal); in PPCTargetLowering()
1239 setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal); in PPCTargetLowering()
1240 setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal); in PPCTargetLowering()
1241 setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal); in PPCTargetLowering()
1242 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal); in PPCTargetLowering()
1243 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal); in PPCTargetLowering()
1244 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal); in PPCTargetLowering()
1245 setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal); in PPCTargetLowering()
1246 setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal); in PPCTargetLowering()
1247 setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal); in PPCTargetLowering()
1248 setOperationAction(ISD::STRICT_FCEIL, MVT::f128, Legal); in PPCTargetLowering()
1249 setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal); in PPCTargetLowering()
1250 setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal); in PPCTargetLowering()
1251 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom); in PPCTargetLowering()
1252 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal); in PPCTargetLowering()
1253 setOperationAction(ISD::BSWAP, MVT::v4i32, Legal); in PPCTargetLowering()
1254 setOperationAction(ISD::BSWAP, MVT::v2i64, Legal); in PPCTargetLowering()
1255 setOperationAction(ISD::BSWAP, MVT::v1i128, Legal); in PPCTargetLowering()
1257 setOperationAction(ISD::LOAD, MVT::f128, Promote); in PPCTargetLowering()
1258 setOperationAction(ISD::STORE, MVT::f128, Promote); in PPCTargetLowering()
1260 AddPromotedToType(ISD::LOAD, MVT::f128, MVT::v4i32); in PPCTargetLowering()
1261 AddPromotedToType(ISD::STORE, MVT::f128, MVT::v4i32); in PPCTargetLowering()
1265 setOperationAction(ISD::FADD, MVT::f128, LibCall); in PPCTargetLowering()
1266 setOperationAction(ISD::FSUB, MVT::f128, LibCall); in PPCTargetLowering()
1268 setOperationAction(ISD::FMUL, MVT::f128, Expand); in PPCTargetLowering()
1269 setOperationAction(ISD::FDIV, MVT::f128, Expand); in PPCTargetLowering()
1270 setOperationAction(ISD::FNEG, MVT::f128, Expand); in PPCTargetLowering()
1271 setOperationAction(ISD::FABS, MVT::f128, Expand); in PPCTargetLowering()
1272 setOperationAction(ISD::FSQRT, MVT::f128, Expand); in PPCTargetLowering()
1273 setOperationAction(ISD::FMA, MVT::f128, Expand); in PPCTargetLowering()
1274 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); in PPCTargetLowering()
1277 setOperationAction(ISD::FP_EXTEND, MVT::f128, Expand); in PPCTargetLowering()
1278 setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Expand); in PPCTargetLowering()
1281 for (MVT VT : {MVT::f32, MVT::f64}) { in PPCTargetLowering()
1286 setOperationAction(ISD::SETCC, MVT::f128, Custom); in PPCTargetLowering()
1287 setOperationAction(ISD::STRICT_FSETCC, MVT::f128, Custom); in PPCTargetLowering()
1288 setOperationAction(ISD::STRICT_FSETCCS, MVT::f128, Custom); in PPCTargetLowering()
1289 setOperationAction(ISD::BR_CC, MVT::f128, Expand); in PPCTargetLowering()
1293 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in PPCTargetLowering()
1296 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); in PPCTargetLowering()
1297 setOperationAction(ISD::SELECT_CC, MVT::i64, isPPC64 ? Custom : Expand); in PPCTargetLowering()
1302 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); in PPCTargetLowering()
1303 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Legal); in PPCTargetLowering()
1304 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Legal); in PPCTargetLowering()
1305 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal); in PPCTargetLowering()
1307 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); in PPCTargetLowering()
1308 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); in PPCTargetLowering()
1310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal); in PPCTargetLowering()
1311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); in PPCTargetLowering()
1312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); in PPCTargetLowering()
1313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); in PPCTargetLowering()
1314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); in PPCTargetLowering()
1315 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); in PPCTargetLowering()
1316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); in PPCTargetLowering()
1318 setOperationAction(ISD::ABDU, MVT::v16i8, Legal); in PPCTargetLowering()
1319 setOperationAction(ISD::ABDU, MVT::v8i16, Legal); in PPCTargetLowering()
1320 setOperationAction(ISD::ABDU, MVT::v4i32, Legal); in PPCTargetLowering()
1321 setOperationAction(ISD::ABDS, MVT::v4i32, Legal); in PPCTargetLowering()
1325 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); in PPCTargetLowering()
1330 addRegisterClass(MVT::v256i1, &PPC::VSRpRCRegClass); in PPCTargetLowering()
1331 setOperationAction(ISD::LOAD, MVT::v256i1, Custom); in PPCTargetLowering()
1332 setOperationAction(ISD::STORE, MVT::v256i1, Custom); in PPCTargetLowering()
1336 addRegisterClass(MVT::v512i1, &PPC::WACCRCRegClass); in PPCTargetLowering()
1338 addRegisterClass(MVT::v512i1, &PPC::UACCRCRegClass); in PPCTargetLowering()
1339 setOperationAction(ISD::LOAD, MVT::v512i1, Custom); in PPCTargetLowering()
1340 setOperationAction(ISD::STORE, MVT::v512i1, Custom); in PPCTargetLowering()
1341 setOperationAction(ISD::BUILD_VECTOR, MVT::v512i1, Custom); in PPCTargetLowering()
1345 setOperationAction(ISD::PREFETCH, MVT::Other, Legal); in PPCTargetLowering()
1348 setOperationAction(ISD::SRA, MVT::v1i128, Legal); in PPCTargetLowering()
1350 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); in PPCTargetLowering()
1353 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); in PPCTargetLowering()
1354 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); in PPCTargetLowering()
1358 setOperationAction(ISD::ATOMIC_LOAD, MVT::i128, Custom); in PPCTargetLowering()
1359 setOperationAction(ISD::ATOMIC_STORE, MVT::i128, Custom); in PPCTargetLowering()
1360 setOperationAction(ISD::INTRINSIC_VOID, MVT::i128, Custom); in PPCTargetLowering()
1842 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32; in getSetCCResultType()
1994 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
2104 if (N->getValueType(0) != MVT::v16i8) in isVMerge()
2162 if (N->getValueType(0) != MVT::v16i8) in isVSLDOIShuffleMask()
2206 if (VT == MVT::v2i64 || VT == MVT::v2f64) in isSplatShuffleMask()
2209 assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) && in isSplatShuffleMask()
2353 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXSLDWIShuffleMask()
2414 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXBRShuffleMaskHelper()
2452 assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); in isXXPERMDIShuffleMask()
2512 if (VT == MVT::v2i64 || VT == MVT::v2f64) in getSplatIdxForPPCMnemonics()
2568 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef in get_VSPLTI_elt()
2571 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2575 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef in get_VSPLTI_elt()
2578 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2600 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); in get_VSPLTI_elt()
2622 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32); in get_VSPLTI_elt()
2639 if (N->getValueType(0) == MVT::i32) in isIntS16Immediate()
2670 if (Memop->getMemoryVT() == MVT::f64) { in SelectAddressEVXRegReg()
2758 if (VT != MVT::i64) in fixupFuncForFI()
2868 if ((CN->getValueType(0) == MVT::i32 || in SelectAddressRegImm()
2875 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32); in SelectAddressRegImm()
2878 MVT::i32); in SelectAddressRegImm()
2879 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectAddressRegImm()
2900 if (N.getValueType() != MVT::i64) in SelectAddressRegImm34()
3011 case MVT::i64: in usePartialVectorLoads()
3013 case MVT::i32: in usePartialVectorLoads()
3017 case MVT::i16: in usePartialVectorLoads()
3018 case MVT::i8: in usePartialVectorLoads()
3099 if (VT != MVT::i64) { in getPreIndexedAddressParts()
3114 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && in getPreIndexedAddressParts()
3174 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; in getTOCEntry()
3181 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT, in getTOCEntry()
3383 TLSReg = DAG.getRegister(PPC::X13, MVT::i64); in LowerGlobalTLSAddressAIX()
3457 SDValue TLSReg = DAG.getRegister(PPC::X13, MVT::i64); in LowerGlobalTLSAddressLinux()
3469 SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64) in LowerGlobalTLSAddressLinux()
3470 : DAG.getRegister(PPC::R2, MVT::i32); in LowerGlobalTLSAddressLinux()
3485 TPOffset = DAG.getLoad(MVT::i64, dl, DAG.getEntryNode(), MatPCRel, in LowerGlobalTLSAddressLinux()
3491 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3518 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3544 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); in LowerGlobalTLSAddressLinux()
3579 SDValue Load = DAG.getLoad(MVT::i64, DL, DAG.getEntryNode(), MatPCRel, in LowerGlobalAddress()
3623 if (LHSVT == MVT::f128) { in LowerSETCC()
3638 if (Op.getValueType() == MVT::v2i64) { in LowerSETCC()
3641 if (LHS.getValueType() == MVT::v2i64) { in LowerSETCC()
3647 dl, MVT::v4i32, DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, LHS), in LowerSETCC()
3648 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, RHS), CC); in LowerSETCC()
3651 DAG.getVectorShuffle(MVT::v4i32, dl, SetCC32, SetCC32, ShuffV); in LowerSETCC()
3652 return DAG.getBitcast(MVT::v2i64, in LowerSETCC()
3654 dl, MVT::v4i32, Shuff, SetCC32)); in LowerSETCC()
3700 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
3701 VAListPtr, MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
3704 if (VT == MVT::i64) { in LowerVAARG()
3706 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, in LowerVAARG()
3707 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
3708 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, in LowerVAARG()
3709 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE); in LowerVAARG()
3710 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, in LowerVAARG()
3711 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
3713 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, in LowerVAARG()
3719 DAG.getConstant(1, dl, MVT::i32)); in LowerVAARG()
3722 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, in LowerVAARG()
3723 FprPtr, MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
3727 DAG.getConstant(8, dl, MVT::i32)); in LowerVAARG()
3730 DAG.getConstant(4, dl, MVT::i32)); in LowerVAARG()
3734 DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, MachinePointerInfo()); in LowerVAARG()
3738 DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, MachinePointerInfo()); in LowerVAARG()
3742 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, in LowerVAARG()
3743 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT); in LowerVAARG()
3746 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, in LowerVAARG()
3749 MVT::i32)); in LowerVAARG()
3758 DAG.getConstant(32, dl, MVT::i32)); in LowerVAARG()
3761 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, in LowerVAARG()
3763 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl, in LowerVAARG()
3764 MVT::i32)); in LowerVAARG()
3768 MachinePointerInfo(SV), MVT::i8); in LowerVAARG()
3776 dl, MVT::i32)); in LowerVAARG()
3778 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, in LowerVAARG()
3782 MachinePointerInfo(), MVT::i32); in LowerVAARG()
3793 DAG.getConstant(12, SDLoc(Op), MVT::i32), Align(8), in LowerVACOPY()
3822 if (Op.getOperand(NumOps - 1).getValueType() == MVT::Glue) in LowerINLINEASM()
3869 bool isPPC64 = (PtrVT == MVT::i64); in LowerINIT_TRAMPOLINE()
3880 isPPC64 ? MVT::i64 : MVT::i32); in LowerINIT_TRAMPOLINE()
3936 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32); in LowerVASTART()
3937 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32); in LowerVASTART()
3957 MachinePointerInfo(SV), MVT::i8); in LowerVASTART()
3965 MachinePointerInfo(SV, nextOffset), MVT::i8); in LowerVASTART()
4010 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotAlignment()
4011 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotAlignment()
4012 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotAlignment()
4013 ArgVT == MVT::v1i128 || ArgVT == MVT::f128) in CalculateStackSlotAlignment()
4033 if (Flags.isSplit() && OrigVT != MVT::ppcf128) in CalculateStackSlotAlignment()
4074 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) in CalculateStackSlotUsed()
4079 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || in CalculateStackSlotUsed()
4080 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || in CalculateStackSlotUsed()
4081 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || in CalculateStackSlotUsed()
4082 ArgVT == MVT::v1i128 || ArgVT == MVT::f128) in CalculateStackSlotUsed()
4183 case MVT::i1: in LowerFormalArguments_32SVR4()
4184 case MVT::i32: in LowerFormalArguments_32SVR4()
4187 case MVT::f32: in LowerFormalArguments_32SVR4()
4195 case MVT::f64: in LowerFormalArguments_32SVR4()
4204 case MVT::v16i8: in LowerFormalArguments_32SVR4()
4205 case MVT::v8i16: in LowerFormalArguments_32SVR4()
4206 case MVT::v4i32: in LowerFormalArguments_32SVR4()
4209 case MVT::v4f32: in LowerFormalArguments_32SVR4()
4212 case MVT::v2f64: in LowerFormalArguments_32SVR4()
4213 case MVT::v2i64: in LowerFormalArguments_32SVR4()
4221 if (VA.getLocVT() == MVT::f64 && Subtarget.hasSPE()) { in LowerFormalArguments_32SVR4()
4225 SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32); in LowerFormalArguments_32SVR4()
4226 SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32); in LowerFormalArguments_32SVR4()
4229 ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo, in LowerFormalArguments_32SVR4()
4234 ValVT == MVT::i1 ? MVT::i32 : ValVT); in LowerFormalArguments_32SVR4()
4235 if (ValVT == MVT::i1) in LowerFormalArguments_32SVR4()
4236 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue); in LowerFormalArguments_32SVR4()
4309 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8; in LowerFormalArguments_32SVR4()
4346 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); in LowerFormalArguments_32SVR4()
4351 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl, in LowerFormalArguments_32SVR4()
4358 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_32SVR4()
4370 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
4373 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, in extendArgForPPC64()
4574 case MVT::i1: in LowerFormalArguments_64SVR4()
4575 case MVT::i32: in LowerFormalArguments_64SVR4()
4576 case MVT::i64: in LowerFormalArguments_64SVR4()
4580 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
4582 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
4594 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
4596 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1) in LowerFormalArguments_64SVR4()
4611 case MVT::f32: in LowerFormalArguments_64SVR4()
4612 case MVT::f64: in LowerFormalArguments_64SVR4()
4619 if (ObjectVT == MVT::f32) in LowerFormalArguments_64SVR4()
4640 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); in LowerFormalArguments_64SVR4()
4642 if (ObjectVT == MVT::f32) { in LowerFormalArguments_64SVR4()
4644 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal, in LowerFormalArguments_64SVR4()
4645 DAG.getConstant(32, dl, MVT::i32)); in LowerFormalArguments_64SVR4()
4646 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); in LowerFormalArguments_64SVR4()
4667 case MVT::v4f32: in LowerFormalArguments_64SVR4()
4668 case MVT::v4i32: in LowerFormalArguments_64SVR4()
4669 case MVT::v8i16: in LowerFormalArguments_64SVR4()
4670 case MVT::v16i8: in LowerFormalArguments_64SVR4()
4671 case MVT::v2f64: in LowerFormalArguments_64SVR4()
4672 case MVT::v2i64: in LowerFormalArguments_64SVR4()
4673 case MVT::v1i128: in LowerFormalArguments_64SVR4()
4674 case MVT::f128: in LowerFormalArguments_64SVR4()
4750 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_64SVR4()
5113 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in EmitTailCallStoreFPAndRetAddr()
5130 EVT VT = isPPC64 ? MVT::i64 : MVT::i32; in CalculateTailCallArgDest()
5147 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in EmitTailCallLoadFPAndRetAddr()
5164 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
5182 StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerMemOpCallTo()
5184 StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerMemOpCallTo()
5208 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2); in PrepareTailCall()
5251 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerCallResult()
5252 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5257 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, in LowerCallResult()
5263 Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi); in LowerCallResult()
5418 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); in transformCallee()
5476 if (LastValue.getValueType() != MVT::Glue) in getOutputChainFromCallSeq()
5488 EVT ReturnTypes[] = {MVT::Other, MVT::Glue}; in prepareIndirectCall()
5544 const MVT RegVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in prepareDescriptorIndirectCall()
5596 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in buildCallOperands()
5639 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32)); in buildCallOperands()
5656 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32)); in buildCallOperands()
5715 SDValue Ret = DAG.getNode(CallOpc, dl, MVT::Other, Ops); in FinishCall()
5720 std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}}; in FinishCall()
5909 MVT ArgVT = Outs[i].VT; in LowerCall_32SVR4()
5966 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_32SVR4()
6024 if (Arg.getValueType() == MVT::i1) in LowerCall_32SVR4()
6026 dl, MVT::i32, Arg); in LowerCall_32SVR4()
6031 if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) { in LowerCall_32SVR4()
6033 SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, in LowerCall_32SVR4()
6036 SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, in LowerCall_32SVR4()
6063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_32SVR4()
6077 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); in LowerCall_32SVR4()
6209 case MVT::i1: in LowerCall_64SVR4()
6210 case MVT::i32: in LowerCall_64SVR4()
6211 case MVT::i64: in LowerCall_64SVR4()
6215 case MVT::v4i32: in LowerCall_64SVR4()
6216 case MVT::v8i16: in LowerCall_64SVR4()
6217 case MVT::v16i8: in LowerCall_64SVR4()
6218 case MVT::v2f64: in LowerCall_64SVR4()
6219 case MVT::v2i64: in LowerCall_64SVR4()
6220 case MVT::v1i128: in LowerCall_64SVR4()
6221 case MVT::f128: in LowerCall_64SVR4()
6225 case MVT::v4f32: in LowerCall_64SVR4()
6229 case MVT::f32: in LowerCall_64SVR4()
6230 case MVT::f64: in LowerCall_64SVR4()
6294 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64); in LowerCall_64SVR4()
6339 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) { in LowerCall_64SVR4()
6342 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); in LowerCall_64SVR4()
6366 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); in LowerCall_64SVR4()
6456 case MVT::i1: in LowerCall_64SVR4()
6457 case MVT::i32: in LowerCall_64SVR4()
6458 case MVT::i64: in LowerCall_64SVR4()
6485 case MVT::f32: in LowerCall_64SVR4()
6486 case MVT::f64: { in LowerCall_64SVR4()
6516 if (Arg.getValueType() != MVT::f32) { in LowerCall_64SVR4()
6517 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); in LowerCall_64SVR4()
6521 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6522 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
6528 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]); in LowerCall_64SVR4()
6529 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6532 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
6536 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall_64SVR4()
6537 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal); in LowerCall_64SVR4()
6539 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal, in LowerCall_64SVR4()
6540 DAG.getConstant(32, dl, MVT::i32)); in LowerCall_64SVR4()
6555 if (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
6573 ArgOffset += (Arg.getValueType() == MVT::f32 && in LowerCall_64SVR4()
6580 case MVT::v4f32: in LowerCall_64SVR4()
6581 case MVT::v4i32: in LowerCall_64SVR4()
6582 case MVT::v8i16: in LowerCall_64SVR4()
6583 case MVT::v16i8: in LowerCall_64SVR4()
6584 case MVT::v2f64: in LowerCall_64SVR4()
6585 case MVT::v2i64: in LowerCall_64SVR4()
6586 case MVT::v1i128: in LowerCall_64SVR4()
6587 case MVT::f128: in LowerCall_64SVR4()
6606 DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, MachinePointerInfo()); in LowerCall_64SVR4()
6651 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_64SVR4()
6663 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64); in LowerCall_64SVR4()
6729 static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT, in CC_AIX()
6737 const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; in CC_AIX()
6739 if (ValVT == MVT::f128) in CC_AIX()
6767 State.addLoc(CCValAssign::getMem(ValNo, MVT::INVALID_SIMPLE_VALUE_TYPE, in CC_AIX()
6779 State.addLoc(CCValAssign::getMem(ValNo, MVT::INVALID_SIMPLE_VALUE_TYPE, in CC_AIX()
6780 Offset, MVT::INVALID_SIMPLE_VALUE_TYPE, in CC_AIX()
6792 case MVT::i64: in CC_AIX()
6796 case MVT::i1: in CC_AIX()
6797 case MVT::i32: { in CC_AIX()
6810 case MVT::f32: in CC_AIX()
6811 case MVT::f64: { in CC_AIX()
6851 case MVT::v4f32: in CC_AIX()
6852 case MVT::v4i32: in CC_AIX()
6853 case MVT::v8i16: in CC_AIX()
6854 case MVT::v16i8: in CC_AIX()
6855 case MVT::v2i64: in CC_AIX()
6856 case MVT::v2f64: in CC_AIX()
6857 case MVT::v1i128: { in CC_AIX()
6956 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT, in getRegClassForSVT()
6960 assert((IsPPC64 || SVT != MVT::i64) && in getRegClassForSVT()
6966 case MVT::i1: in getRegClassForSVT()
6967 case MVT::i32: in getRegClassForSVT()
6968 case MVT::i64: in getRegClassForSVT()
6970 case MVT::f32: in getRegClassForSVT()
6972 case MVT::f64: in getRegClassForSVT()
6974 case MVT::v4f32: in getRegClassForSVT()
6975 case MVT::v4i32: in getRegClassForSVT()
6976 case MVT::v8i16: in getRegClassForSVT()
6977 case MVT::v16i8: in getRegClassForSVT()
6978 case MVT::v2i64: in getRegClassForSVT()
6979 case MVT::v2f64: in getRegClassForSVT()
6980 case MVT::v1i128: in getRegClassForSVT()
6987 MVT LocVT, const SDLoc &dl) { in truncateScalarIntegerArg()
7096 MVT LocVT = VA.getLocVT(); in LowerFormalArguments_AIX()
7097 MVT ValVT = VA.getValVT(); in LowerFormalArguments_AIX()
7147 MVT::SimpleValueType SVT = VA.getLocVT().SimpleTy; in LowerFormalArguments_AIX()
7179 case MVT::f32: in LowerFormalArguments_AIX()
7182 case MVT::f64: in LowerFormalArguments_AIX()
7190 case MVT::v16i8: in LowerFormalArguments_AIX()
7193 case MVT::v8i16: in LowerFormalArguments_AIX()
7196 case MVT::v4i32: in LowerFormalArguments_AIX()
7197 case MVT::v2i64: in LowerFormalArguments_AIX()
7198 case MVT::v1i128: in LowerFormalArguments_AIX()
7201 case MVT::v4f32: in LowerFormalArguments_AIX()
7202 case MVT::v2f64: in LowerFormalArguments_AIX()
7288 MVT::SimpleValueType SVT = ValVT.SimpleTy; in LowerFormalArguments_AIX()
7356 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps); in LowerFormalArguments_AIX()
7418 const SDValue StackPtr = IsPPC64 ? DAG.getRegister(PPC::X1, MVT::i64) in LowerCall_AIX()
7419 : DAG.getRegister(PPC::R1, MVT::i32); in LowerCall_AIX()
7491 const MVT VT = in LowerCall_AIX()
7492 N == 1 ? MVT::i8 in LowerCall_AIX()
7493 : ((N == 2) ? MVT::i16 : (N == 4 ? MVT::i32 : MVT::i64)); in LowerCall_AIX()
7522 const MVT LocVT = VA.getLocVT(); in LowerCall_AIX()
7523 const MVT ValVT = VA.getValVT(); in LowerCall_AIX()
7610 DAG.getBitcast(MVT::getIntegerVT(ValVT.getSizeInBits()), Arg); in LowerCall_AIX()
7624 assert(Arg.getValueType() == MVT::f64 && CFlags.IsVarArg && !IsPPC64 && in LowerCall_AIX()
7627 SDValue MSWAsI64 = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgAsInt, in LowerCall_AIX()
7628 DAG.getConstant(32, dl, MVT::i8)); in LowerCall_AIX()
7630 GPR1.getLocReg(), DAG.getZExtOrTrunc(MSWAsI64, dl, MVT::i32))); in LowerCall_AIX()
7640 GPR2.getLocReg(), DAG.getZExtOrTrunc(ArgAsInt, dl, MVT::i32))); in LowerCall_AIX()
7647 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains); in LowerCall_AIX()
7655 const MVT PtrVT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerCall_AIX()
7732 if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { in LowerReturn()
7736 DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, in LowerReturn()
7740 SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, in LowerReturn()
7757 return DAG.getNode(PPCISD::RET_GLUE, dl, MVT::Other, RetOps); in LowerReturn()
7866 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); in LowerDYNAMIC_STACKALLOC()
7887 DAG.getVTList(MVT::i32, MVT::Other), in lowerEH_SJLJ_SETJMP()
7894 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, in lowerEH_SJLJ_LONGJMP()
7902 assert(Op.getValueType() == MVT::i1 && in LowerLOAD()
7916 BasePtr, MVT::i8, MMO); in LowerLOAD()
7917 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD); in LowerLOAD()
7927 assert(Op.getOperand(1).getValueType() == MVT::i1 && in LowerSTORE()
7942 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO); in LowerSTORE()
7947 assert(Op.getValueType() == MVT::i1 && in LowerTRUNCATE()
7951 return DAG.getNode(PPCISD::ANDI_rec_1_GT_BIT, DL, MVT::i1, Op.getOperand(0)); in LowerTRUNCATE()
8048 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { in LowerSELECT_CC()
8084 ResVT == MVT::f128) in LowerSELECT_CC()
8097 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8098 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8100 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8101 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
8103 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
8110 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8111 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8119 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8120 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); in LowerSELECT_CC()
8122 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); in LowerSELECT_CC()
8133 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8134 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8136 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8137 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); in LowerSELECT_CC()
8139 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
8143 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8144 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8149 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8150 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8155 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8156 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8161 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits in LowerSELECT_CC()
8162 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); in LowerSELECT_CC()
8205 MVT DestTy = Op.getSimpleValueType(); in convertFPToInt()
8207 (DestTy == MVT::i8 || DestTy == MVT::i16 || DestTy == MVT::i32 || in convertFPToInt()
8208 DestTy == MVT::i64) && in convertFPToInt()
8210 if (Src.getValueType() == MVT::f32) { in convertFPToInt()
8214 DAG.getVTList(MVT::f64, MVT::Other), {Chain, Src}, Flags); in convertFPToInt()
8217 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in convertFPToInt()
8219 if ((DestTy == MVT::i8 || DestTy == MVT::i16) && Subtarget.hasP9Vector()) in convertFPToInt()
8220 DestTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in convertFPToInt()
8224 case MVT::i32: in convertFPToInt()
8228 case MVT::i64: in convertFPToInt()
8233 EVT ConvTy = Src.getValueType() == MVT::f128 ? MVT::f128 : MVT::f64; in convertFPToInt()
8237 Conv = DAG.getNode(Opc, dl, DAG.getVTList(ConvTy, MVT::Other), {Chain, Src}, in convertFPToInt()
8254 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() && in LowerFP_TO_INTForReuse()
8256 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64); in LowerFP_TO_INTForReuse()
8271 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO); in LowerFP_TO_INTForReuse()
8277 if (Op.getValueType() == MVT::i32 && !i32Stack) { in LowerFP_TO_INTForReuse()
8313 if (SrcVT == MVT::f128) in LowerFP_TO_INT()
8318 if (SrcVT == MVT::ppcf128) { in LowerFP_TO_INT()
8319 if (DstVT == MVT::i32) { in LowerFP_TO_INT()
8328 std::tie(Lo, Hi) = DAG.SplitScalar(Src, dl, MVT::f64, MVT::f64); in LowerFP_TO_INT()
8334 DAG.getVTList(MVT::f64, MVT::Other), in LowerFP_TO_INT()
8337 DAG.getVTList(MVT::i32, MVT::Other), in LowerFP_TO_INT()
8340 SDValue Res = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi); in LowerFP_TO_INT()
8341 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in LowerFP_TO_INT()
8367 DAG.getVTList(SrcVT, MVT::Other), in LowerFP_TO_INT()
8371 DAG.getVTList(DstVT, MVT::Other), in LowerFP_TO_INT()
8381 SDValue True = DAG.getNode(ISD::FSUB, dl, MVT::ppcf128, Src, Cst); in LowerFP_TO_INT()
8382 True = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, True); in LowerFP_TO_INT()
8383 True = DAG.getNode(ISD::ADD, dl, MVT::i32, True, SignMask); in LowerFP_TO_INT()
8384 SDValue False = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Src); in LowerFP_TO_INT()
8421 (Subtarget.hasFPCVT() || Op.getValueType() == MVT::i32); in canReuseLoadAddress()
8477 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in spliceIntoChain()
8478 NewResChain, DAG.getUNDEF(MVT::Other)); in spliceIntoChain()
8531 bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT(); in convertIntToFP()
8534 EVT ConvTy = IsSingle ? MVT::f32 : MVT::f64; in convertIntToFP()
8539 DAG.getVTList(ConvTy, MVT::Other), {Chain, Src}, Flags); in convertIntToFP()
8550 assert((Op.getValueType() == MVT::f32 || in LowerINT_TO_FPDirectMove()
8551 Op.getValueType() == MVT::f64) && in LowerINT_TO_FPDirectMove()
8556 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32; in LowerINT_TO_FPDirectMove()
8560 SDValue Mov = DAG.getNode(MovOpc, dl, MVT::f64, Src); in LowerINT_TO_FPDirectMove()
8592 assert((Op.getValueType() == MVT::v2f64 || Op.getValueType() == MVT::v4f32) && in LowerINT_TO_FPVector()
8600 bool FourEltRes = Op.getValueType() == MVT::v4f32; in LowerINT_TO_FPVector()
8605 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector()
8638 return DAG.getNode(Opc, dl, DAG.getVTList(Op.getValueType(), MVT::Other), in LowerINT_TO_FPVector()
8664 if (Op.getValueType() == MVT::f128) in LowerINT_TO_FP()
8668 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in LowerINT_TO_FP()
8671 if (Src.getValueType() == MVT::i1) { in LowerINT_TO_FP()
8690 if (Src.getValueType() == MVT::i64) { in LowerINT_TO_FP()
8702 if (Op.getValueType() == MVT::f32 && in LowerINT_TO_FP()
8712 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
8713 SINT, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
8714 Round = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
8715 Round, DAG.getConstant(2047, dl, MVT::i64)); in LowerINT_TO_FP()
8716 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); in LowerINT_TO_FP()
8717 Round = DAG.getNode(ISD::AND, dl, MVT::i64, in LowerINT_TO_FP()
8718 Round, DAG.getConstant(-2048, dl, MVT::i64)); in LowerINT_TO_FP()
8728 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, in LowerINT_TO_FP()
8729 SINT, DAG.getConstant(53, dl, MVT::i32)); in LowerINT_TO_FP()
8730 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, in LowerINT_TO_FP()
8731 Cond, DAG.getConstant(1, dl, MVT::i64)); in LowerINT_TO_FP()
8734 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64), in LowerINT_TO_FP()
8735 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT); in LowerINT_TO_FP()
8737 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT); in LowerINT_TO_FP()
8744 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) { in LowerINT_TO_FP()
8745 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, in LowerINT_TO_FP()
8749 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) { in LowerINT_TO_FP()
8755 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
8756 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
8759 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { in LowerINT_TO_FP()
8765 DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
8766 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
8772 SINT.getOperand(0).getValueType() == MVT::i32) { in LowerINT_TO_FP()
8784 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
8799 dl, DAG.getVTList(MVT::f64, MVT::Other), in LowerINT_TO_FP()
8800 Ops, MVT::i32, MMO); in LowerINT_TO_FP()
8803 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); in LowerINT_TO_FP()
8809 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8812 DAG.getVTList(MVT::f32, MVT::Other), in LowerINT_TO_FP()
8815 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8821 assert(Src.getValueType() == MVT::i32 && in LowerINT_TO_FP()
8835 if (!(ReusingLoad = canReuseLoadAddress(Src, MVT::i32, RLI, DAG))) { in LowerINT_TO_FP()
8844 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 && in LowerINT_TO_FP()
8859 DAG.getVTList(MVT::f64, MVT::Other), Ops, in LowerINT_TO_FP()
8860 MVT::i32, MMO); in LowerINT_TO_FP()
8871 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64, Src); in LowerINT_TO_FP()
8881 MVT::f64, dl, Chain, FIdx, in LowerINT_TO_FP()
8890 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in LowerINT_TO_FP()
8893 DAG.getVTList(MVT::f32, MVT::Other), in LowerINT_TO_FP()
8896 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in LowerINT_TO_FP()
8930 SDValue MFFS = DAG.getNode(PPCISD::MFFS, dl, {MVT::f64, MVT::Other}, Chain); in LowerGET_ROUNDING()
8934 if (isTypeLegal(MVT::i64)) { in LowerGET_ROUNDING()
8935 CWD = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, in LowerGET_ROUNDING()
8936 DAG.getNode(ISD::BITCAST, dl, MVT::i64, MFFS)); in LowerGET_ROUNDING()
8944 assert(hasBigEndianPartOrdering(MVT::i64, MF.getDataLayout()) && in LowerGET_ROUNDING()
8948 CWD = DAG.getLoad(MVT::i32, dl, Chain, Addr, MachinePointerInfo()); in LowerGET_ROUNDING()
8954 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerGET_ROUNDING()
8955 CWD, DAG.getConstant(3, dl, MVT::i32)); in LowerGET_ROUNDING()
8957 DAG.getNode(ISD::SRL, dl, MVT::i32, in LowerGET_ROUNDING()
8958 DAG.getNode(ISD::AND, dl, MVT::i32, in LowerGET_ROUNDING()
8959 DAG.getNode(ISD::XOR, dl, MVT::i32, in LowerGET_ROUNDING()
8960 CWD, DAG.getConstant(3, dl, MVT::i32)), in LowerGET_ROUNDING()
8961 DAG.getConstant(3, dl, MVT::i32)), in LowerGET_ROUNDING()
8962 DAG.getConstant(1, dl, MVT::i32)); in LowerGET_ROUNDING()
8965 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); in LowerGET_ROUNDING()
9094 static const MVT VTys[] = { // canonical VT to use for each size. in getCanonicalConstSplat()
9095 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 in getCanonicalConstSplat()
9098 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; in getCanonicalConstSplat()
9115 const SDLoc &dl, EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
9116 if (DestVT == MVT::Other) DestVT = Op.getValueType(); in BuildIntrinsicOp()
9118 DAG.getConstant(IID, dl, MVT::i32), Op); in BuildIntrinsicOp()
9125 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
9126 if (DestVT == MVT::Other) DestVT = LHS.getValueType(); in BuildIntrinsicOp()
9128 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS); in BuildIntrinsicOp()
9135 EVT DestVT = MVT::Other) { in BuildIntrinsicOp()
9136 if (DestVT == MVT::Other) DestVT = Op0.getValueType(); in BuildIntrinsicOp()
9138 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2); in BuildIntrinsicOp()
9146 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); in BuildVSLDOI()
9147 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); in BuildVSLDOI()
9152 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); in BuildVSLDOI()
9172 bool RightType = VecVT == MVT::v2f64 || in haveEfficientBuildVectorPattern()
9173 (HasP8Vector && VecVT == MVT::v4f32) || in haveEfficientBuildVectorPattern()
9174 (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32)); in haveEfficientBuildVectorPattern()
9215 if ((Op.getValueType() != MVT::f128) || in LowerBITCAST()
9217 (Op0.getOperand(0).getValueType() != MVT::i64) || in LowerBITCAST()
9218 (Op0.getOperand(1).getValueType() != MVT::i64)) in LowerBITCAST()
9221 return DAG.getNode(PPCISD::BUILD_FP128, dl, MVT::f128, Op0.getOperand(0), in LowerBITCAST()
9289 if ((Ty == MVT::v2f64 || Ty == MVT::v4f32 || Ty == MVT::v4i32) && in isValidSplatLoad()
9298 if ((Ty == MVT::v8i16 || Ty == MVT::v16i8) && ISD::isEXTLoad(InputNode) && in isValidSplatLoad()
9302 if (Ty == MVT::v2i64) { in isValidSplatLoad()
9305 if (MemVT == MVT::i32) { in isValidSplatLoad()
9343 if ((Op->getValueType(0) == MVT::v2f64) && in LowerBUILD_VECTOR()
9346 PPCISD::XXSPLTI_SP_TO_DP, dl, MVT::v2f64, in LowerBUILD_VECTOR()
9347 DAG.getTargetConstant(APSplatBits.getZExtValue(), dl, MVT::i32)); in LowerBUILD_VECTOR()
9356 SDValue SplatNode = DAG.getUNDEF(MVT::v2i64); in LowerBUILD_VECTOR()
9360 SplatNode = DAG.getTargetConstant(0, dl, MVT::v2i64); in LowerBUILD_VECTOR()
9364 PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode, in LowerBUILD_VECTOR()
9365 DAG.getTargetConstant(0, dl, MVT::i32), in LowerBUILD_VECTOR()
9366 DAG.getTargetConstant(Hi, dl, MVT::i32)); in LowerBUILD_VECTOR()
9370 DAG.getNode(PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode, in LowerBUILD_VECTOR()
9371 DAG.getTargetConstant(1, dl, MVT::i32), in LowerBUILD_VECTOR()
9372 DAG.getTargetConstant(Lo, dl, MVT::i32)); in LowerBUILD_VECTOR()
9421 (Op->getValueType(0) == MVT::v2i64 && NewOpcode != PPCISD::LD_SPLAT && in LowerBUILD_VECTOR()
9444 NewOpcode, dl, DAG.getVTList(Op.getValueType(), MVT::Other), Ops, in LowerBUILD_VECTOR()
9473 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { in LowerBUILD_VECTOR()
9474 SDValue Z = DAG.getConstant(0, dl, MVT::v4i32); in LowerBUILD_VECTOR()
9518 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32); in LowerBUILD_VECTOR()
9519 EVT VT = (SplatSize == 1 ? MVT::v16i8 : in LowerBUILD_VECTOR()
9520 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); in LowerBUILD_VECTOR()
9521 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32); in LowerBUILD_VECTOR()
9534 SDValue OnesV = getCanonicalConstSplat(-1, 4, MVT::v4i32, DAG, dl); in LowerBUILD_VECTOR()
9541 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); in LowerBUILD_VECTOR()
9562 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
9573 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
9585 SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); in LowerBUILD_VECTOR()
9596 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
9602 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
9608 SDValue T = getCanonicalConstSplat(i, SplatSize, MVT::v16i8, DAG, dl); in LowerBUILD_VECTOR()
9688 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS); in GeneratePerfectShuffle()
9689 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS); in GeneratePerfectShuffle()
9690 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); in GeneratePerfectShuffle()
9786 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2, in lowerToVINSERTB()
9787 DAG.getConstant(ShiftElts, dl, MVT::i32)); in lowerToVINSERTB()
9788 return DAG.getNode(PPCISD::VECINSERT, dl, MVT::v16i8, V1, Shl, in lowerToVINSERTB()
9789 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTB()
9791 return DAG.getNode(PPCISD::VECINSERT, dl, MVT::v16i8, V1, V2, in lowerToVINSERTB()
9792 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTB()
9891 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); in lowerToVINSERTH()
9894 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v16i8, V2, V2, in lowerToVINSERTH()
9895 DAG.getConstant(2 * ShiftElts, dl, MVT::i32)); in lowerToVINSERTH()
9896 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, Shl); in lowerToVINSERTH()
9897 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2, in lowerToVINSERTH()
9898 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTH()
9899 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in lowerToVINSERTH()
9901 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); in lowerToVINSERTH()
9902 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v8i16, Conv1, Conv2, in lowerToVINSERTH()
9903 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in lowerToVINSERTH()
9904 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in lowerToVINSERTH()
9961 Index = DAG.getTargetConstant(IsLE ? 0 : 1, DL, MVT::i32); in lowerToXXSPLTI32DX()
9965 Index = DAG.getTargetConstant(IsLE ? 1 : 0, DL, MVT::i32); in lowerToXXSPLTI32DX()
9976 PPCISD::XXSPLTI32DX, DL, MVT::v2i64, DAG.getBitcast(MVT::v2i64, LHS), in lowerToXXSPLTI32DX()
9977 Index, DAG.getTargetConstant(SplatVal, DL, MVT::i32)); in lowerToXXSPLTI32DX()
9978 return DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, SplatNode); in lowerToXXSPLTI32DX()
9987 assert(Op.getValueType() == MVT::v1i128 && in LowerROTL()
9998 DAG.getVectorShuffle(MVT::v16i8, dl, DAG.getBitcast(MVT::v16i8, N0), in LowerROTL()
9999 DAG.getUNDEF(MVT::v16i8), Mask)) in LowerROTL()
10000 return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, Shuffle); in LowerROTL()
10002 SDValue ArgVal = DAG.getBitcast(MVT::i128, N0); in LowerROTL()
10003 SDValue SHLOp = DAG.getNode(ISD::SHL, dl, MVT::i128, ArgVal, in LowerROTL()
10004 DAG.getConstant(SHLAmt, dl, MVT::i32)); in LowerROTL()
10005 SDValue SRLOp = DAG.getNode(ISD::SRL, dl, MVT::i128, ArgVal, in LowerROTL()
10006 DAG.getConstant(128 - SHLAmt, dl, MVT::i32)); in LowerROTL()
10007 SDValue OROp = DAG.getNode(ISD::OR, dl, MVT::i128, SHLOp, SRLOp); in LowerROTL()
10008 return DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, OROp); in LowerROTL()
10086 DAG.getVTList(IsFourByte ? MVT::v4i32 : MVT::v2i64, MVT::Other); in LowerVECTOR_SHUFFLE()
10098 if (VT == MVT::v2i64 || VT == MVT::v2f64) in LowerVECTOR_SHUFFLE()
10106 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
10107 SDValue Conv2 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2); in LowerVECTOR_SHUFFLE()
10109 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv2, Conv2, in LowerVECTOR_SHUFFLE()
10110 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10111 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Shl, in LowerVECTOR_SHUFFLE()
10112 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10113 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in LowerVECTOR_SHUFFLE()
10115 SDValue Ins = DAG.getNode(PPCISD::VECINSERT, dl, MVT::v4i32, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
10116 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10117 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Ins); in LowerVECTOR_SHUFFLE()
10139 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
10141 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2.isUndef() ? V1 : V2); in LowerVECTOR_SHUFFLE()
10143 SDValue Shl = DAG.getNode(PPCISD::VECSHL, dl, MVT::v4i32, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
10144 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10145 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Shl); in LowerVECTOR_SHUFFLE()
10152 SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1); in LowerVECTOR_SHUFFLE()
10154 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2.isUndef() ? V1 : V2); in LowerVECTOR_SHUFFLE()
10156 SDValue PermDI = DAG.getNode(PPCISD::XXPERMDI, dl, MVT::v2i64, Conv1, Conv2, in LowerVECTOR_SHUFFLE()
10157 DAG.getConstant(ShiftElts, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10158 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, PermDI); in LowerVECTOR_SHUFFLE()
10163 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); in LowerVECTOR_SHUFFLE()
10164 SDValue ReveHWord = DAG.getNode(ISD::BSWAP, dl, MVT::v8i16, Conv); in LowerVECTOR_SHUFFLE()
10165 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveHWord); in LowerVECTOR_SHUFFLE()
10167 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
10168 SDValue ReveWord = DAG.getNode(ISD::BSWAP, dl, MVT::v4i32, Conv); in LowerVECTOR_SHUFFLE()
10169 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveWord); in LowerVECTOR_SHUFFLE()
10171 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1); in LowerVECTOR_SHUFFLE()
10172 SDValue ReveDWord = DAG.getNode(ISD::BSWAP, dl, MVT::v2i64, Conv); in LowerVECTOR_SHUFFLE()
10173 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveDWord); in LowerVECTOR_SHUFFLE()
10175 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v1i128, V1); in LowerVECTOR_SHUFFLE()
10176 SDValue ReveQWord = DAG.getNode(ISD::BSWAP, dl, MVT::v1i128, Conv); in LowerVECTOR_SHUFFLE()
10177 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveQWord); in LowerVECTOR_SHUFFLE()
10185 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1); in LowerVECTOR_SHUFFLE()
10186 SDValue Splat = DAG.getNode(PPCISD::XXSPLT, dl, MVT::v4i32, Conv, in LowerVECTOR_SHUFFLE()
10187 DAG.getConstant(SplatIdx, dl, MVT::i32)); in LowerVECTOR_SHUFFLE()
10188 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Splat); in LowerVECTOR_SHUFFLE()
10193 SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); in LowerVECTOR_SHUFFLE()
10194 SDValue Swap = DAG.getNode(PPCISD::SWAP_NO_CHAIN, dl, MVT::v2f64, Conv); in LowerVECTOR_SHUFFLE()
10195 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, Swap); in LowerVECTOR_SHUFFLE()
10388 DAG.getConstant(31 - (SrcElt * BytesPerElement + j), dl, MVT::i32)); in LowerVPERM()
10391 DAG.getConstant(SrcElt * BytesPerElement + j, dl, MVT::i32)); in LowerVPERM()
10404 if (ValType != MVT::v2f64) in LowerVPERM()
10405 V1 = DAG.getBitcast(MVT::v2f64, V1); in LowerVPERM()
10406 if (V2.getValueType() != MVT::v2f64) in LowerVPERM()
10407 V2 = DAG.getBitcast(MVT::v2f64, V2); in LowerVPERM()
10411 SDValue VPermMask = DAG.getBuildVector(MVT::v16i8, dl, ResultMask); in LowerVPERM()
10425 VPermMask = DAG.getBitcast(MVT::v4i32, VPermMask); in LowerVPERM()
10737 return DAG.getRegister(PPC::X13, MVT::i64); in LowerINTRINSIC_WO_CHAIN()
10738 return DAG.getRegister(PPC::R2, MVT::i32); in LowerINTRINSIC_WO_CHAIN()
10742 EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1}; in LowerINTRINSIC_WO_CHAIN()
10753 PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, in LowerINTRINSIC_WO_CHAIN()
10759 PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, in LowerINTRINSIC_WO_CHAIN()
10765 PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, in LowerINTRINSIC_WO_CHAIN()
10771 PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, in LowerINTRINSIC_WO_CHAIN()
10785 WideVec = DAG.getNode(PPCISD::XXMFACC, dl, MVT::v512i1, WideVec); in LowerINTRINSIC_WO_CHAIN()
10790 PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, WideVec, in LowerINTRINSIC_WO_CHAIN()
10817 return DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::f64, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
10843 PPC::SELECT_CC_I4, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
10844 {SDValue(DAG.getMachineNode(PPC::XSCMPEXPDP, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
10847 DAG.getConstant(1, dl, MVT::i32), DAG.getConstant(0, dl, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
10848 DAG.getTargetConstant(Pred, dl, MVT::i32)}), in LowerINTRINSIC_WO_CHAIN()
10853 unsigned CmprOpc = OpVT == MVT::f128 ? PPC::XSTSTDCQP in LowerINTRINSIC_WO_CHAIN()
10854 : (OpVT == MVT::f64 ? PPC::XSTSTDCDP in LowerINTRINSIC_WO_CHAIN()
10858 PPC::SELECT_CC_I4, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
10859 {SDValue(DAG.getMachineNode(CmprOpc, dl, MVT::i32, Op.getOperand(2), in LowerINTRINSIC_WO_CHAIN()
10862 DAG.getConstant(1, dl, MVT::i32), DAG.getConstant(0, dl, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
10863 DAG.getTargetConstant(PPC::PRED_EQ, dl, MVT::i32)}), in LowerINTRINSIC_WO_CHAIN()
10868 if (!Subtarget.hasVSX() || (!Subtarget.hasFloat128() && VT == MVT::f128)) in LowerINTRINSIC_WO_CHAIN()
10925 DAG.getConstant(CompareOpc, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
10933 DAG.getConstant(CompareOpc, dl, MVT::i32) in LowerINTRINSIC_WO_CHAIN()
10935 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue }; in LowerINTRINSIC_WO_CHAIN()
10940 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
10941 DAG.getRegister(PPC::CR6, MVT::i32), in LowerINTRINSIC_WO_CHAIN()
10964 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
10965 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
10967 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
10968 DAG.getConstant(1, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
10972 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, in LowerINTRINSIC_WO_CHAIN()
10973 DAG.getConstant(1, dl, MVT::i32)); in LowerINTRINSIC_WO_CHAIN()
10988 if (Ty == MVT::i128) { in LowerINTRINSIC_VOID()
10991 Val = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, Val); in LowerINTRINSIC_VOID()
10994 EVT FTy = Subtarget.isPPC64() ? MVT::i64 : MVT::i32; in LowerINTRINSIC_VOID()
10996 DAG.getMachineNode(Opcode, DL, MVT::Other, in LowerINTRINSIC_VOID()
11013 Op = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, Op.getOperand(0), in LowerBSWAP()
11016 Op = DAG.getNode(ISD::BSWAP, dl, MVT::v2i64, Op); in LowerBSWAP()
11021 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Op, in LowerBSWAP()
11022 DAG.getTargetConstant(VectorIndex, dl, MVT::i32)); in LowerBSWAP()
11047 DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp, in LowerATOMIC_CMP_SWAP()
11048 DAG.getConstant(MaskVal, dl, MVT::i32)); in LowerATOMIC_CMP_SWAP()
11056 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::Other); in LowerATOMIC_CMP_SWAP()
11058 (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16; in LowerATOMIC_CMP_SWAP()
11066 assert(MemVT.getSimpleVT() == MVT::i128 && in LowerATOMIC_LOAD_STORE()
11074 SDVTList Tys = DAG.getVTList(MVT::i64, MVT::i64, MVT::Other); in LowerATOMIC_LOAD_STORE()
11077 DAG.getConstant(Intrinsic::ppc_atomic_load_i128, dl, MVT::i32)}; in LowerATOMIC_LOAD_STORE()
11082 SDValue ValLo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i128, LoadedVal); in LowerATOMIC_LOAD_STORE()
11084 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i128, LoadedVal.getValue(1)); in LowerATOMIC_LOAD_STORE()
11085 ValHi = DAG.getNode(ISD::SHL, dl, MVT::i128, ValHi, in LowerATOMIC_LOAD_STORE()
11086 DAG.getConstant(64, dl, MVT::i32)); in LowerATOMIC_LOAD_STORE()
11088 DAG.getNode(ISD::OR, dl, {MVT::i128, MVT::Other}, {ValLo, ValHi}); in LowerATOMIC_LOAD_STORE()
11089 return DAG.getNode(ISD::MERGE_VALUES, dl, {MVT::i128, MVT::Other}, in LowerATOMIC_LOAD_STORE()
11095 SDVTList Tys = DAG.getVTList(MVT::Other); in LowerATOMIC_LOAD_STORE()
11098 DAG.getConstant(Intrinsic::ppc_atomic_store_i128, dl, MVT::i32)}; in LowerATOMIC_LOAD_STORE()
11100 SDValue ValLo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i64, Val); in LowerATOMIC_LOAD_STORE()
11101 SDValue ValHi = DAG.getNode(ISD::SRL, dl, MVT::i128, Val, in LowerATOMIC_LOAD_STORE()
11102 DAG.getConstant(64, dl, MVT::i32)); in LowerATOMIC_LOAD_STORE()
11103 ValHi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i64, ValHi); in LowerATOMIC_LOAD_STORE()
11132 unsigned TestOp = VT == MVT::f128 ? PPC::XSTSTDCQP in getDataClassTest()
11133 : VT == MVT::f64 ? PPC::XSTSTDCDP in getDataClassTest()
11137 return DAG.getBoolConstant(true, Dl, MVT::i1, VT); in getDataClassTest()
11139 return DAG.getBoolConstant(false, Dl, MVT::i1, VT); in getDataClassTest()
11144 return DAG.getNOT(Dl, Rev, MVT::i1); in getDataClassTest()
11151 TestOp, Dl, MVT::i32, in getDataClassTest()
11155 Dl, MVT::i32), in getDataClassTest()
11160 DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, Dl, MVT::i1, Rev, in getDataClassTest()
11161 DAG.getTargetConstant(PPC::sub_lt, Dl, MVT::i32)), in getDataClassTest()
11166 TargetOpcode::EXTRACT_SUBREG, Dl, MVT::i1, Rev, in getDataClassTest()
11167 DAG.getTargetConstant(PPC::sub_eq, Dl, MVT::i32)), in getDataClassTest()
11169 MVT::i1)); in getDataClassTest()
11171 Sign = DAG.getNOT(Dl, Sign, MVT::i1); in getDataClassTest()
11172 SDValue Result = DAG.getNode(ISD::AND, Dl, MVT::i1, Sign, Normal); in getDataClassTest()
11177 ISD::OR, Dl, MVT::i1, in getDataClassTest()
11190 if (VT == MVT::f128) { in getDataClassTest()
11192 ISD::EXTRACT_VECTOR_ELT, Dl, MVT::i32, DAG.getBitcast(MVT::v4i32, Op), in getDataClassTest()
11195 } else if (VT == MVT::f64) { in getDataClassTest()
11197 HighWord = DAG.getNode(ISD::EXTRACT_ELEMENT, Dl, MVT::i32, in getDataClassTest()
11198 DAG.getBitcast(MVT::i64, Op), in getDataClassTest()
11199 DAG.getConstant(1, Dl, MVT::i32)); in getDataClassTest()
11202 MVT::v4i32, DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v2f64, Op)); in getDataClassTest()
11204 ISD::EXTRACT_VECTOR_ELT, Dl, MVT::i32, Vec, in getDataClassTest()
11208 } else if (VT == MVT::f32) { in getDataClassTest()
11209 HighWord = DAG.getBitcast(MVT::i32, Op); in getDataClassTest()
11213 Dl, MVT::i1, in getDataClassTest()
11214 DAG.getNode(ISD::AND, Dl, MVT::i32, HighWord, in getDataClassTest()
11215 DAG.getConstant(QuietMask, Dl, MVT::i32)), in getDataClassTest()
11216 DAG.getConstant(0, Dl, MVT::i32), IsQuiet ? ISD::SETNE : ISD::SETEQ); in getDataClassTest()
11217 NanRes = DAG.getNode(ISD::AND, Dl, MVT::i1, NanCheck, NanRes); in getDataClassTest()
11221 return DAG.getNode(ISD::OR, Dl, MVT::i1, in getDataClassTest()
11243 TargetOpcode::EXTRACT_SUBREG, Dl, MVT::i1, in getDataClassTest()
11245 TestOp, Dl, MVT::i32, in getDataClassTest()
11246 DAG.getTargetConstant(NativeMask, Dl, MVT::i32), Op), in getDataClassTest()
11248 DAG.getTargetConstant(PPC::sub_eq, Dl, MVT::i32)), in getDataClassTest()
11290 if (VT == MVT::v2f64 && C) in LowerINSERT_VECTOR_ELT()
11302 if ((VT == MVT::v4f32) && (V2.getValueType() == MVT::f32) && in LowerINSERT_VECTOR_ELT()
11304 SDValue BitcastVector = DAG.getBitcast(MVT::v4i32, V1); in LowerINSERT_VECTOR_ELT()
11305 SDValue BitcastLoad = DAG.getBitcast(MVT::i32, V2); in LowerINSERT_VECTOR_ELT()
11307 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v4i32, BitcastVector, in LowerINSERT_VECTOR_ELT()
11309 return DAG.getBitcast(MVT::v4f32, InsVecElt); in LowerINSERT_VECTOR_ELT()
11314 if ((VT == MVT::v2i64 || VT == MVT::v2f64) && !Subtarget.isPPC64()) in LowerINSERT_VECTOR_ELT()
11318 if (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || in LowerINSERT_VECTOR_ELT()
11319 VT == MVT::v2i64 || VT == MVT::v4f32 || VT == MVT::v2f64) in LowerINSERT_VECTOR_ELT()
11329 if (VT == MVT::v8i16 || VT == MVT::v16i8) { in LowerINSERT_VECTOR_ELT()
11338 DAG.getConstant(InsertAtByte, dl, MVT::i32)); in LowerINSERT_VECTOR_ELT()
11351 if (VT != MVT::v256i1 && VT != MVT::v512i1) in LowerVectorLoad()
11357 assert((VT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorLoad()
11359 assert((VT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorLoad()
11367 DAG.getLoad(MVT::v16i8, dl, LoadChain, BasePtr, in LowerVectorLoad()
11380 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains); in LowerVectorLoad()
11382 DAG.getNode(VT == MVT::v512i1 ? PPCISD::ACC_BUILD : PPCISD::PAIR_BUILD, in LowerVectorLoad()
11398 if (StoreVT != MVT::v256i1 && StoreVT != MVT::v512i1) in LowerVectorStore()
11404 assert((StoreVT != MVT::v512i1 || Subtarget.hasMMA()) && in LowerVectorStore()
11406 assert((StoreVT != MVT::v256i1 || Subtarget.pairedVectorMemops()) && in LowerVectorStore()
11411 if (StoreVT == MVT::v512i1) { in LowerVectorStore()
11413 EVT ReturnTypes[] = {MVT::v256i1, MVT::v256i1}; in LowerVectorStore()
11420 Value = DAG.getNode(PPCISD::XXMFACC, dl, MVT::v512i1, Value); in LowerVectorStore()
11428 Elt = DAG.getNode(PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, in LowerVectorStore()
11432 Elt = DAG.getNode(PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, Value, in LowerVectorStore()
11450 if (Op.getValueType() == MVT::v4i32) { in LowerMUL()
11453 SDValue Zero = getCanonicalConstSplat(0, 1, MVT::v4i32, DAG, dl); in LowerMUL()
11455 SDValue Neg16 = getCanonicalConstSplat(-16, 4, MVT::v4i32, DAG, dl); in LowerMUL()
11460 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); in LowerMUL()
11461 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS); in LowerMUL()
11462 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap); in LowerMUL()
11467 LHS, RHS, DAG, dl, MVT::v4i32); in LowerMUL()
11470 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); in LowerMUL()
11474 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); in LowerMUL()
11475 } else if (Op.getValueType() == MVT::v16i8) { in LowerMUL()
11481 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
11482 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); in LowerMUL()
11486 LHS, RHS, DAG, dl, MVT::v8i16); in LowerMUL()
11487 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); in LowerMUL()
11504 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops); in LowerMUL()
11506 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); in LowerMUL()
11514 if (Op.getOperand(IsStrict ? 1 : 0).getValueType() == MVT::f128 && in LowerFP_ROUND()
11529 if (Op.getValueType() != MVT::v2f64 || in LowerFP_EXTEND()
11530 Op.getOperand(0).getValueType() != MVT::v2f32) in LowerFP_EXTEND()
11544 if (Op0.getOperand(0).getValueType() != MVT::v4f32) in LowerFP_EXTEND()
11560 return DAG.getNode(PPCISD::FP_EXTEND_HALF, dl, MVT::v2f64, in LowerFP_EXTEND()
11561 Op0.getOperand(0), DAG.getConstant(DWord, dl, MVT::i32)); in LowerFP_EXTEND()
11576 PPCISD::LD_VSX_LH, dl, DAG.getVTList(MVT::v4f32, MVT::Other), LoadOps, in LowerFP_EXTEND()
11580 DAG.getNode(Op0.getOpcode(), SDLoc(Op0), MVT::v4f32, NewLoad[0], in LowerFP_EXTEND()
11582 return DAG.getNode(PPCISD::FP_EXTEND_HALF, dl, MVT::v2f64, NewOp, in LowerFP_EXTEND()
11583 DAG.getConstant(0, dl, MVT::i32)); in LowerFP_EXTEND()
11589 PPCISD::LD_VSX_LH, dl, DAG.getVTList(MVT::v4f32, MVT::Other), LoadOps, in LowerFP_EXTEND()
11591 return DAG.getNode(PPCISD::FP_EXTEND_HALF, dl, MVT::v2f64, NewLd, in LowerFP_EXTEND()
11592 DAG.getConstant(0, dl, MVT::i32)); in LowerFP_EXTEND()
11708 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); in ReplaceNodeResults()
11712 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, RTB, RTB.getValue(1))); in ReplaceNodeResults()
11720 assert(N->getValueType(0) == MVT::i1 && in ReplaceNodeResults()
11724 SDVTList VTs = DAG.getVTList(SVT, MVT::Other); in ReplaceNodeResults()
11728 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewInt)); in ReplaceNodeResults()
11735 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
11753 if (VT == MVT::i64) { in ReplaceNodeResults()
11767 MVT::ppcf128) in ReplaceNodeResults()
12244 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
12248 MVT PVT = getPointerTy(MF->getDataLayout()); in emitEHSjLjSetJmp()
12249 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjSetJmp()
12380 MVT PVT = getPointerTy(MF->getDataLayout()); in emitEHSjLjLongJmp()
12381 assert((PVT == MVT::i64 || PVT == MVT::i32) && in emitEHSjLjLongJmp()
12385 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; in emitEHSjLjLongJmp()
12388 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; in emitEHSjLjLongJmp()
12389 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; in emitEHSjLjLongJmp()
12391 (PVT == MVT::i64) in emitEHSjLjLongJmp()
12408 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
12420 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
12432 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
12444 if (PVT == MVT::i64) { in emitEHSjLjLongJmp()
12456 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) { in emitEHSjLjLongJmp()
12466 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); in emitEHSjLjLongJmp()
12467 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); in emitEHSjLjLongJmp()
13484 if (VT.getScalarType() == MVT::f64) in getEstimateRefinementSteps()
13493 if (!isTypeLegal(MVT::i1) || in getSqrtInputTest()
13494 (VT != MVT::f64 && in getSqrtInputTest()
13495 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX()))) in getSqrtInputTest()
13500 SDValue FTSQRT = DAG.getNode(PPCISD::FTSQRT, DL, MVT::i32, Op); in getSqrtInputTest()
13512 SDValue SRIdxVal = DAG.getTargetConstant(PPC::sub_eq, DL, MVT::i32); in getSqrtInputTest()
13513 return SDValue(DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::i1, in getSqrtInputTest()
13523 if (VT != MVT::f64 && in getSqrtResultForDenormInput()
13524 ((VT != MVT::v2f64 && VT != MVT::v4f32) || !Subtarget.hasVSX())) in getSqrtResultForDenormInput()
13535 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) || in getSqrtEstimate()
13536 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) || in getSqrtEstimate()
13537 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getSqrtEstimate()
13538 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getSqrtEstimate()
13554 if ((VT == MVT::f32 && Subtarget.hasFRES()) || in getRecipEstimate()
13555 (VT == MVT::f64 && Subtarget.hasFRE()) || in getRecipEstimate()
13556 (VT == MVT::v4f32 && Subtarget.hasAltivec()) || in getRecipEstimate()
13557 (VT == MVT::v2f64 && Subtarget.hasVSX())) { in getRecipEstimate()
13659 VT = MVT::v4i32; in isConsecutiveLS()
13663 VT = MVT::v2f64; in isConsecutiveLS()
13666 VT = MVT::i8; in isConsecutiveLS()
13669 VT = MVT::i16; in isConsecutiveLS()
13672 VT = MVT::i32; in isConsecutiveLS()
13686 VT = MVT::v4i32; in isConsecutiveLS()
13689 VT = MVT::v2f64; in isConsecutiveLS()
13692 VT = MVT::v4i32; in isConsecutiveLS()
13695 VT = MVT::v2f64; in isConsecutiveLS()
13698 VT = MVT::i8; in isConsecutiveLS()
13701 VT = MVT::i16; in isConsecutiveLS()
13704 VT = MVT::i32; in isConsecutiveLS()
13791 auto Op0 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(0), in generateEquivalentSub()
13792 DAG.getConstant(Size, DL, MVT::i32)); in generateEquivalentSub()
13793 auto Op1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1), in generateEquivalentSub()
13794 DAG.getConstant(Size, DL, MVT::i32)); in generateEquivalentSub()
13801 auto SubNode = DAG.getNode(ISD::SUB, DL, MVT::i64, Op0, Op1); in generateEquivalentSub()
13805 auto Shifted = DAG.getNode(ISD::SRL, DL, MVT::i64, SubNode, in generateEquivalentSub()
13806 DAG.getConstant(Size - 1, DL, MVT::i32)); in generateEquivalentSub()
13811 Final = DAG.getNode(ISD::XOR, DL, MVT::i64, Shifted, in generateEquivalentSub()
13812 DAG.getConstant(1, DL, MVT::i64)); in generateEquivalentSub()
13814 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Final); in generateEquivalentSub()
13873 N->getValueType(0) != MVT::i1) in DAGCombineTruncBoolExt()
13876 if (N->getOperand(0).getValueType() != MVT::i32 && in DAGCombineTruncBoolExt()
13877 N->getOperand(0).getValueType() != MVT::i64) in DAGCombineTruncBoolExt()
13952 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
13982 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) || in DAGCombineTruncBoolExt()
14079 PromOp.getOperand(0).getValueType() != MVT::i1) { in DAGCombineTruncBoolExt()
14087 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue); in DAGCombineTruncBoolExt()
14101 PromOp.getOperand(C).getValueType() != MVT::i1) || in DAGCombineTruncBoolExt()
14103 PromOp.getOperand(C+1).getValueType() != MVT::i1)) { in DAGCombineTruncBoolExt()
14118 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]); in DAGCombineTruncBoolExt()
14121 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops)); in DAGCombineTruncBoolExt()
14152 if (N->getValueType(0) != MVT::i32 && in DAGCombineExtBoolTrunc()
14153 N->getValueType(0) != MVT::i64) in DAGCombineExtBoolTrunc()
14156 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || in DAGCombineExtBoolTrunc()
14157 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64()))) in DAGCombineExtBoolTrunc()
14444 Op.getValueType() == MVT::f64; in isFPExtLoad()
14514 DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, In.getOperand(0), in combineElementTruncationToVectorTruncation()
14529 EVT NewVT = TargetVT == MVT::v2i64 ? MVT::v2f64 : MVT::v4f32; in combineElementTruncationToVectorTruncation()
14781 if (N->getValueType(0) != MVT::v1i128) in combineBVZEXTLOAD()
14795 bool ValidLDType = MemoryType == MVT::i8 || MemoryType == MVT::i16 || in combineBVZEXTLOAD()
14796 MemoryType == MVT::i32 || MemoryType == MVT::i64; in combineBVZEXTLOAD()
14809 DAG.getVTList(MVT::v1i128, MVT::Other), in combineBVZEXTLOAD()
14859 if (N->getValueType(0) != MVT::v2f64) in DAGCombineBuildVector()
14883 if (Ext1.getOperand(0).getValueType() != MVT::v4i32 || in DAGCombineBuildVector()
14900 return DAG.getNode(NodeType, dl, MVT::v2f64, in DAGCombineBuildVector()
14919 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) in combineFPToIntToFP()
14923 if (Op.getOperand(0).getValueType().getSimpleVT() <= MVT(MVT::i1) || in combineFPToIntToFP()
14924 Op.getOperand(0).getValueType().getSimpleVT() > MVT(MVT::i64)) in combineFPToIntToFP()
14929 (FirstOperand.getValueType() == MVT::i8 || in combineFPToIntToFP()
14930 FirstOperand.getValueType() == MVT::i16); in combineFPToIntToFP()
14933 bool DstDouble = Op.getValueType() == MVT::f64; in combineFPToIntToFP()
14938 DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2, in combineFPToIntToFP()
14943 DAG.getVTList(MVT::f64, MVT::Other), in combineFPToIntToFP()
14944 Ops, MVT::i8, LDN->getMemOperand()); in combineFPToIntToFP()
14950 SDValue Ext = DAG.getNode(PPCISD::VEXTS, dl, MVT::f64, ExtOps); in combineFPToIntToFP()
14951 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ext); in combineFPToIntToFP()
14953 return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld); in combineFPToIntToFP()
14961 if (Op.getOperand(0).getValueType() == MVT::i32) in combineFPToIntToFP()
14969 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14974 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) in combineFPToIntToFP()
14975 ? MVT::f32 in combineFPToIntToFP()
14976 : MVT::f64; in combineFPToIntToFP()
14984 if (Src.getValueType() == MVT::f32) { in combineFPToIntToFP()
14985 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); in combineFPToIntToFP()
14987 } else if (Src.getValueType() != MVT::f64) { in combineFPToIntToFP()
14996 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src); in combineFPToIntToFP()
14999 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { in combineFPToIntToFP()
15000 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, in combineFPToIntToFP()
15052 MVT VecTy = N->getValueType(0).getSimpleVT(); in expandVSXLoadForLE()
15056 DAG.getVTList(MVT::v2f64, MVT::Other), in expandVSXLoadForLE()
15057 LoadOps, MVT::v2f64, MMO); in expandVSXLoadForLE()
15062 PPCISD::XXSWAPD, dl, DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Load); in expandVSXLoadForLE()
15066 if (VecTy != MVT::v2f64) { in expandVSXLoadForLE()
15070 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(VecTy, MVT::Other), in expandVSXLoadForLE()
15121 MVT VecTy = Src.getValueType().getSimpleVT(); in expandVSXStoreForLE()
15124 if (VecTy != MVT::v2f64) { in expandVSXStoreForLE()
15125 Src = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Src); in expandVSXStoreForLE()
15130 DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src); in expandVSXStoreForLE()
15135 DAG.getVTList(MVT::Other), in expandVSXStoreForLE()
15163 (Op1VT == MVT::i32 || (Op1VT == MVT::i64 && Subtarget.isPPC64()) || in combineStoreFPToInt()
15164 (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); in combineStoreFPToInt()
15167 if (ResVT == MVT::ppcf128 || (ResVT == MVT::f128 && !Subtarget.hasP9Vector())) in combineStoreFPToInt()
15170 if ((Op1VT != MVT::i64 && !Subtarget.hasP8Vector()) || in combineStoreFPToInt()
15183 DAG.getVTList(MVT::Other), Ops, in combineStoreFPToInt()
15527 PPCISD::LOAD_VEC_BE, dl, DAG.getVTList(VT, MVT::Other), LoadOps, in combineVReverseMemOP()
15542 PPCISD::STORE_VEC_BE, dl, DAG.getVTList(MVT::Other), StoreOps, in combineVReverseMemOP()
15580 !isa<ConstantSDNode>(Op2) || N->getValueType(0) != MVT::i64 || in PerformDAGCombine()
15581 Op1.getOperand(0).getValueType() != MVT::i32) in PerformDAGCombine()
15592 SDValue ConstOp = DAG.getConstant(Imm, dl, MVT::i32); in PerformDAGCombine()
15593 SDValue NarrowAnd = DAG.getNode(ISD::AND, dl, MVT::i32, NarrowOp, ConstOp); in PerformDAGCombine()
15665 (Op1VT == MVT::i32 || Op1VT == MVT::i16 || in PerformDAGCombine()
15666 (Subtarget.hasLDBRX() && Subtarget.isPPC64() && Op1VT == MVT::i64))) { in PerformDAGCombine()
15676 if (BSwapOp.getValueType() == MVT::i16) in PerformDAGCombine()
15677 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); in PerformDAGCombine()
15684 DAG.getConstant(Shift, dl, MVT::i32)); in PerformDAGCombine()
15686 if (Op1VT == MVT::i64) in PerformDAGCombine()
15687 BSwapOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BSwapOp); in PerformDAGCombine()
15694 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), in PerformDAGCombine()
15702 isa<ConstantSDNode>(N->getOperand(1)) && Op1VT == MVT::i32) { in PerformDAGCombine()
15707 SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64); in PerformDAGCombine()
15721 MVT StoreVT = Op1VT.getSimpleVT(); in PerformDAGCombine()
15723 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 || in PerformDAGCombine()
15724 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32)) in PerformDAGCombine()
15736 MVT LoadVT = VT.getSimpleVT(); in PerformDAGCombine()
15738 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 || in PerformDAGCombine()
15739 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32)) in PerformDAGCombine()
15751 if (VT != MVT::i64) in PerformDAGCombine()
15778 Trunc->getValueType(0) != MVT::i32 || in PerformDAGCombine()
15789 Trunc2->getValueType(0) != MVT::i32 || in PerformDAGCombine()
15797 Bitcast->getValueType(0) != MVT::f32) in PerformDAGCombine()
15800 Bitcast2->getValueType(0) != MVT::f32) in PerformDAGCombine()
15820 SDValue FloatLoad = DAG.getLoad(MVT::f32, dl, LD->getChain(), BasePtr, in PerformDAGCombine()
15827 MVT::f32, dl, SDValue(FloatLoad.getNode(), 1), AddPtr, in PerformDAGCombine()
15855 (VT == MVT::v16i8 || VT == MVT::v8i16 || VT == MVT::v4i32 || in PerformDAGCombine()
15856 VT == MVT::v4f32))) && in PerformDAGCombine()
15888 MVT PermCntlTy, PermTy, LDTy; in PerformDAGCombine()
15893 PermCntlTy = MVT::v16i8; in PerformDAGCombine()
15894 PermTy = MVT::v4i32; in PerformDAGCombine()
15895 LDTy = MVT::v4i32; in PerformDAGCombine()
15916 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
15946 DAG.getVTList(PermTy, MVT::Other), in PerformDAGCombine()
15949 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in PerformDAGCombine()
15969 DAG.getTargetConstant(1, dl, MVT::i64)); in PerformDAGCombine()
16034 if ((V1.getSimpleValueType() == MVT::v4i32 || in PerformDAGCombine()
16035 V1.getSimpleValueType() == MVT::v8i16 || in PerformDAGCombine()
16036 V1.getSimpleValueType() == MVT::v16i8) && in PerformDAGCombine()
16113 Subtarget.isPPC64() && N->getValueType(0) == MVT::i64; in PerformDAGCombine()
16117 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 || in PerformDAGCombine()
16129 DAG.getVTList(N->getValueType(0) == MVT::i64 ? in PerformDAGCombine()
16130 MVT::i64 : MVT::i32, MVT::Other), in PerformDAGCombine()
16135 if (N->getValueType(0) == MVT::i16) in PerformDAGCombine()
16136 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); in PerformDAGCombine()
16160 SDValue Lo = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr, in PerformDAGCombine()
16162 Lo = DAG.getNode(ISD::BSWAP, dl, MVT::i32, Lo); in PerformDAGCombine()
16167 SDValue Hi = DAG.getLoad(MVT::i32, dl, LD->getChain(), BasePtr, NewMMO); in PerformDAGCombine()
16168 Hi = DAG.getNode(ISD::BSWAP, dl, MVT::i32, Hi); in PerformDAGCombine()
16171 Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Hi, Lo); in PerformDAGCombine()
16173 Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
16175 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, in PerformDAGCombine()
16261 return DAG.getNode(ISD::BR, dl, MVT::Other, in PerformDAGCombine()
16283 DAG.getConstant(StoreWidth, dl, MVT::i32)}; in PerformDAGCombine()
16287 DAG.getVTList(MVT::i32, MVT::Other, MVT::Glue), Ops, in PerformDAGCombine()
16300 InChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, InChains); in PerformDAGCombine()
16303 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, InChain, in PerformDAGCombine()
16304 DAG.getConstant(CompOpc, dl, MVT::i32), in PerformDAGCombine()
16305 DAG.getRegister(PPC::CR0, MVT::i32), N->getOperand(4), in PerformDAGCombine()
16321 DAG.getConstant(CompareOpc, dl, MVT::i32) in PerformDAGCombine()
16323 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue }; in PerformDAGCombine()
16344 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), in PerformDAGCombine()
16345 DAG.getConstant(CompOpc, dl, MVT::i32), in PerformDAGCombine()
16346 DAG.getRegister(PPC::CR6, MVT::i32), in PerformDAGCombine()
16364 if (VT == MVT::i64 && !Subtarget.isPPC64()) in BuildSDIVPow2()
16366 if ((VT != MVT::i32 && VT != MVT::i64) || in BuildSDIVPow2()
16402 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16) in computeKnownBitsForTargetNode()
16590 MVT VT) const { in getRegForInlineAsmConstraint()
16595 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16599 if (VT == MVT::i64 && Subtarget.isPPC64()) in getRegForInlineAsmConstraint()
16608 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
16610 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
16613 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
16615 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
16639 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16643 if (VT == MVT::f32 && Subtarget.hasP8Vector()) in getRegForInlineAsmConstraint()
16648 if (VT == MVT::i64) in getRegForInlineAsmConstraint()
16675 if (VT == MVT::f32 || VT == MVT::i32) in getRegForInlineAsmConstraint()
16679 if (VT == MVT::f64 || VT == MVT::i64) in getRegForInlineAsmConstraint()
16695 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && in getRegForInlineAsmConstraint()
16746 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative in LowerAsmOperandForConstraint()
16887 isPPC64 ? MVT::i64 : MVT::i32); in LowerRETURNADDR()
16909 bool isPPC64 = PtrVT == MVT::i64; in LowerFRAMEADDR()
16994 Info.memVT = MVT::i128; in getTgtMemIntrinsic()
17003 Info.memVT = MVT::i128; in getTgtMemIntrinsic()
17011 Info.memVT = MVT::i128; in getTgtMemIntrinsic()
17031 VT = MVT::i8; in getTgtMemIntrinsic()
17034 VT = MVT::i16; in getTgtMemIntrinsic()
17037 VT = MVT::i32; in getTgtMemIntrinsic()
17041 VT = MVT::v2f64; in getTgtMemIntrinsic()
17044 VT = MVT::v4i32; in getTgtMemIntrinsic()
17071 VT = MVT::i8; in getTgtMemIntrinsic()
17074 VT = MVT::i16; in getTgtMemIntrinsic()
17077 VT = MVT::i32; in getTgtMemIntrinsic()
17081 VT = MVT::v2f64; in getTgtMemIntrinsic()
17084 VT = MVT::v4i32; in getTgtMemIntrinsic()
17105 VT = MVT::i64; in getTgtMemIntrinsic()
17108 VT = MVT::i32; in getTgtMemIntrinsic()
17112 VT = MVT::i16; in getTgtMemIntrinsic()
17116 VT = MVT::i8; in getTgtMemIntrinsic()
17149 return MVT::v8i16; in getOptimalMemOpType()
17151 return MVT::v4i32; in getOptimalMemOpType()
17154 return MVT::v4i32; in getOptimalMemOpType()
17159 return MVT::i64; in getOptimalMemOpType()
17162 return MVT::i32; in getOptimalMemOpType()
17196 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 || in isZExtFree()
17197 (Subtarget.isPPC64() && MemVT == MVT::i32)) && in isZExtFree()
17215 if (DestVT == MVT::f128) in isFPExtFree()
17249 if (VT != MVT::v2f64 && VT != MVT::v2i64 && in allowsMisalignedMemoryAccesses()
17250 VT != MVT::v4f32 && VT != MVT::v4i32) in allowsMisalignedMemoryAccesses()
17257 if (VT == MVT::ppcf128) in allowsMisalignedMemoryAccesses()
17392 if (VT == MVT::v2i64) in shouldExpandBuildVectorWithShuffles()
17528 case MVT::f32: in isFPImmLegal()
17529 case MVT::f64: { in isFPImmLegal()
17544 case MVT::ppcf128: in isFPImmLegal()
17591 N0.getOperand(0).getValueType() != MVT::i32 || CN1 == nullptr || in combineSHL()
17592 N->getValueType(0) != MVT::i64) in combineSHL()
17606 if (ShiftBy.getValueType() == MVT::i64) in combineSHL()
17607 ShiftBy = DCI.DAG.getConstant(CN1->getZExtValue(), DL, MVT::i32); in combineSHL()
17609 return DCI.DAG.getNode(PPCISD::EXTSWSLI, DL, MVT::i64, N0->getOperand(0), in combineSHL()
17641 Op.getValueType() != MVT::i64) in combineADDToADDZE()
17646 Cmp.getOperand(0).getValueType() != MVT::i64) in combineADDToADDZE()
17669 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Glue); in combineADDToADDZE()
17684 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z, in combineADDToADDZE()
17685 DAG.getConstant(NegConstant, DL, MVT::i64)); in combineADDToADDZE()
17687 SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue), in combineADDToADDZE()
17688 AddOrZ, DAG.getConstant(-1ULL, DL, MVT::i64)); in combineADDToADDZE()
17689 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
17699 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z, in combineADDToADDZE()
17700 DAG.getConstant(NegConstant, DL, MVT::i64)); in combineADDToADDZE()
17702 SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue), in combineADDToADDZE()
17703 DAG.getConstant(0, DL, MVT::i64), AddOrZ); in combineADDToADDZE()
17704 return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), in combineADDToADDZE()
17790 if (Op0.getValueType() != MVT::i128 || N->getValueType(0) != MVT::i64) in combineTRUNCATE()
17810 Op0.getValueType() == MVT::i128 && in combineTRUNCATE()
17811 Op0.getOperand(0).getValueType() == MVT::f128) { in combineTRUNCATE()
17812 SDValue Bitcast = DCI.DAG.getBitcast(MVT::v2i64, Op0.getOperand(0)); in combineTRUNCATE()
17814 ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Bitcast, in combineTRUNCATE()
17815 DCI.DAG.getTargetConstant(EltToExtract, dl, MVT::i32)); in combineTRUNCATE()
18176 else if (MemVT == MVT::f128 || MemVT.isVector()) in computeMOFlags()
18260 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts()
18266 if (PartVT == MVT::f64 && in splitValueIntoRegisterParts()
18267 (ValVT == MVT::i32 || ValVT == MVT::i16 || ValVT == MVT::i8)) { in splitValueIntoRegisterParts()
18268 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val); in splitValueIntoRegisterParts()
18269 Val = DAG.getNode(ISD::BITCAST, DL, MVT::f64, Val); in splitValueIntoRegisterParts()
18318 if (Op.getValueType() == MVT::f32) in lowerLibCallBasedOnType()
18321 if (Op.getValueType() == MVT::f64) in lowerLibCallBasedOnType()
18477 if ((CNType == MVT::i32 || isInt<32>(CNImm)) && in SelectOptimalAddrMode()
18481 Disp = DAG.getTargetConstant((int16_t)Addr, DL, MVT::i32); in SelectOptimalAddrMode()
18483 DAG.getTargetConstant((Addr - (int16_t)Addr) >> 16, DL, MVT::i32); in SelectOptimalAddrMode()
18484 uint32_t LIS = CNType == MVT::i32 ? PPC::LIS : PPC::LIS8; in SelectOptimalAddrMode()