5594   const bool IsPPC64 = Subtarget.isPPC64();  in buildCallOperands()  local
5596   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;  in buildCallOperands()
5634       Ops.push_back(DAG.getRegister(IsPPC64 ? PPC::CTR8 : PPC::CTR, RegVT));  in buildCallOperands()
6735   const bool IsPPC64 = Subtarget.isPPC64();  in CC_AIX()  local
6736   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);  in CC_AIX()
6737   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;  in CC_AIX()
6776       if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32))  in CC_AIX()
6794     assert(IsPPC64 && "PPC32 should have split i64 values.");  in CC_AIX()
6803     if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32))  in CC_AIX()
6817         State.AllocateStack(IsPPC64 ? 8 : StoreSize, Align(4));  in CC_AIX()
6824       if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) {  in CC_AIX()
6876     const unsigned PtrSize = IsPPC64 ? 8 : 4;  in CC_AIX()
6877     ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32;  in CC_AIX()
6957                                                     bool IsPPC64,  in getRegClassForSVT()  argument
6960   assert((IsPPC64 || SVT != MVT::i64) &&  in getRegClassForSVT()
6969     return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;  in getRegClassForSVT()
7076   const bool IsPPC64 = Subtarget.isPPC64();  in LowerFormalArguments_AIX()  local
7077   const unsigned PtrByteSize = IsPPC64 ? 8 : 4;  in LowerFormalArguments_AIX()
7149                      getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),  in LowerFormalArguments_AIX()
7163         assert(!IsPPC64 &&  in LowerFormalArguments_AIX()
7240           IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;  in LowerFormalArguments_AIX()
7291                        getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),  in LowerFormalArguments_AIX()
7332     const unsigned NumGPArgRegs = std::size(IsPPC64 ? GPR_64 : GPR_32);  in LowerFormalArguments_AIX()
7342           IsPPC64 ? MF.addLiveIn(GPR_64[GPRIndex], &PPC::G8RCRegClass)  in LowerFormalArguments_AIX()
7391   const bool IsPPC64 = Subtarget.isPPC64();  in LowerCall_AIX()  local
7393   const unsigned PtrByteSize = IsPPC64 ? 8 : 4;  in LowerCall_AIX()
7418   const SDValue StackPtr = IsPPC64 ? DAG.getRegister(PPC::X1, MVT::i64)  in LowerCall_AIX()
7580         assert(!IsPPC64 &&  in LowerCall_AIX()
7624       assert(Arg.getValueType() == MVT::f64 && CFlags.IsVarArg && !IsPPC64 &&  in LowerCall_AIX()