Lines Matching refs:FV
8042 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); in LowerSELECT_CC() local
8053 return DAG.getSelectCC(dl, Z, Zero, TV, FV, ISD::SETNE); in LowerSELECT_CC()
8065 if (Subtarget.hasP9Vector() && LHS == TV && RHS == FV) { in LowerSELECT_CC()
8094 std::swap(TV, FV); in LowerSELECT_CC()
8099 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
8103 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); in LowerSELECT_CC()
8106 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt in LowerSELECT_CC()
8112 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
8115 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt in LowerSELECT_CC()
8122 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); in LowerSELECT_CC()
8129 std::swap(TV, FV); in LowerSELECT_CC()
8135 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8139 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); in LowerSELECT_CC()
8145 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
8151 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8157 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
8163 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()