Lines Matching refs:RBReg
1676 unsigned RBReg = SPReg; in emitEpilogue() local
1719 BuildMI(MBB, MBBI, dl, OrInst, RBReg). in emitEpilogue()
1730 RBReg = FPReg; in emitEpilogue()
1732 BuildMI(MBB, MBBI, dl, AddImmInst, RBReg) in emitEpilogue()
1737 .addReg(RBReg) in emitEpilogue()
1765 RBReg = FPReg; in emitEpilogue()
1767 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, RBReg) in emitEpilogue()
1772 assert(RBReg != ScratchReg && "Should have avoided ScratchReg"); in emitEpilogue()
1796 if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) { in emitEpilogue()
1799 .addReg(RBReg); in emitEpilogue()
1804 assert(RBReg == SPReg && "Should be using SP as a base register"); in emitEpilogue()
1807 .addReg(RBReg); in emitEpilogue()
1813 if (HasRedZone || RBReg == SPReg) in emitEpilogue()
1820 .addReg(RBReg); in emitEpilogue()
1826 .addReg(RBReg); in emitEpilogue()
1831 .addReg(RBReg); in emitEpilogue()
1835 if (RBReg != SPReg || SPAdd != 0) { in emitEpilogue()
1840 .addReg(RBReg) in emitEpilogue()
1841 .addReg(RBReg); in emitEpilogue()
1844 .addReg(RBReg) in emitEpilogue()
1847 assert(RBReg != ScratchReg && "Should be using FP or SP as base register"); in emitEpilogue()
1848 if (RBReg == FPReg) in emitEpilogue()